/*******************************************************************************
*              (c), Copyright 2001, Marvell International Ltd.                 *
* THIS CODE CONTAINS CONFIDENTIAL INFORMATION OF MARVELL SEMICONDUCTOR, INC.   *
* NO RIGHTS ARE GRANTED HEREIN UNDER ANY PATENT, MASK WORK RIGHT OR COPYRIGHT  *
* OF MARVELL OR ANY THIRD PARTY. MARVELL RESERVES THE RIGHT AT ITS SOLE        *
* DISCRETION TO REQUEST THAT THIS CODE BE IMMEDIATELY RETURNED TO MARVELL.     *
* THIS CODE IS PROVIDED "AS IS". MARVELL MAKES NO WARRANTIES, EXPRESSED,       *
* IMPLIED OR OTHERWISE, REGARDING ITS ACCURACY, COMPLETENESS OR PERFORMANCE.   *
********************************************************************************
* prvCpssDrvExMxEventsTiger.h
*
* DESCRIPTION:
*       This file includes all different hardware driven Event types - Tiger
*
*       Applicable devices: Tiger
*                           52 ports - 98EX116 , 98EX106 , 98EX108 , 98EX116DI
*                           12 ports - 98EX126 , 98EX126DI
*                           XG       - 98EX136 , 98EX136DI
*
* FILE REVISION NUMBER:
*       $Revision: 1 $
*
*******************************************************************************/
#ifndef __prvCpssDrvExMxEventsTigerh
#define __prvCpssDrvExMxEventsTigerh

#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */

/*
 * Typedef: enum PRV_CPSS_TG_12_INT_CAUSE
 *
 * Description: All interrupt cause indexes_E, to be used for interrupts handling_E,
 *              and parameters change.
 *
 * NOTE : If needed_E, new interrupt bits can replace the XXX_RES_i bits_E, in case
 *        that these bits fall into the same cause registers.
 *
 *       Applicable devices: Tiger
 *                           12 ports - 98EX126 , 98EX126DI
 *
 * Comment:
 *      Please see the description of each of the following interrupt event
 *      cause registers in the packet processor datasheet.
 */
typedef enum
{
    /* Summary and PCI interrupts   */
    /* Indexes 0 - 31               */
    PRV_CPSS_TG_12_SUM_RES_0_E                       = 0,
    PRV_CPSS_TG_12_MAS_READ_ERR_E,
    PRV_CPSS_TG_12_SLV_WRITE_ERR_E,
    PRV_CPSS_TG_12_MAS_WRITE_ERR_E,
    PRV_CPSS_TG_12_ADDR_ERR_E,
    PRV_CPSS_TG_12_MAS_ABORT_E,
    PRV_CPSS_TG_12_TARGET_ABORT_E,
    PRV_CPSS_TG_12_SLV_READ_ERR_E,
    PRV_CPSS_TG_12_RETRY_CNTR_E,
    PRV_CPSS_TG_12_SUM_RES_9_E,
    PRV_CPSS_TG_12_SUM_RES_10_E,
    PRV_CPSS_TG_12_SUM_RES_11_E,
    PRV_CPSS_TG_12_SUM_RES_12_E,
    PRV_CPSS_TG_12_SUM_RES_13_E,
    PRV_CPSS_TG_12_SUM_RES_14_E,
    PRV_CPSS_TG_12_SUM_RES_15_E,
    PRV_CPSS_TG_12_SUM_RES_16_E,
    PRV_CPSS_TG_12_SUM_RES_17_E,
    PRV_CPSS_TG_12_SUM_RES_18_E,
    PRV_CPSS_TG_12_SUM_RES_19_E,
    PRV_CPSS_TG_12_SUM_RES_20_E,
    PRV_CPSS_TG_12_SUM_RES_21_E,
    PRV_CPSS_TG_12_SUM_RES_22_E,
    PRV_CPSS_TG_12_SUM_RES_23_E,
    PRV_CPSS_TG_12_SUM_RES_24_E,
    PRV_CPSS_TG_12_SUM_RES_25_E,
    PRV_CPSS_TG_12_SUM_RES_26_E,
    PRV_CPSS_TG_12_SUM_RES_27_E,
    PRV_CPSS_TG_12_SUM_RES_28_E,
    PRV_CPSS_TG_12_SUM_RES_29_E,
    PRV_CPSS_TG_12_SUM_RES_30_E,
    PRV_CPSS_TG_12_SUM_RES_31_E,

    /* Ethernet Bridge interrupts   */
    /* Indexes 32 - 63              */
    PRV_CPSS_TG_12_ETH_RES_0_E,
    PRV_CPSS_TG_12_EB_NA_FIFO_FULL_E,
    PRV_CPSS_TG_12_MAC_NUM_OF_HOP_EXP_E,
    PRV_CPSS_TG_12_MAC_AGE_VIA_TRIGGER_ENDED_E,
    PRV_CPSS_TG_12_MAC_NA_LEARNED_E,
    PRV_CPSS_TG_12_MAC_NA_NOT_LEARNED_E,
    PRV_CPSS_TG_12_MAC_TBL_READ_ECC_ERR_E,
    PRV_CPSS_TG_12_EB_MG_ADDR_OUT_OF_RANGE_E,
    PRV_CPSS_TG_12_EB_INGRESS_FILTER_PCKT_E,
    PRV_CPSS_TG_12_EB_NA_NOT_LEARNED_SECURITY_BREACH_E,
    PRV_CPSS_TG_12_ETH_RES_10_E,
    PRV_CPSS_TG_12_ETH_RES_11_E,
    PRV_CPSS_TG_12_ETH_RES_12_E,
    PRV_CPSS_TG_12_ETH_RES_13_E,
    PRV_CPSS_TG_12_ETH_RES_14_E,
    PRV_CPSS_TG_12_ETH_RES_15_E,
    PRV_CPSS_TG_12_ETH_RES_16_E,
    PRV_CPSS_TG_12_ETH_RES_17_E,
    PRV_CPSS_TG_12_ETH_RES_18_E,
    PRV_CPSS_TG_12_ETH_RES_19_E,
    PRV_CPSS_TG_12_ETH_RES_20_E,
    PRV_CPSS_TG_12_ETH_RES_21_E,
    PRV_CPSS_TG_12_ETH_RES_22_E,
    PRV_CPSS_TG_12_ETH_RES_23_E,
    PRV_CPSS_TG_12_ETH_RES_24_E,
    PRV_CPSS_TG_12_ETH_RES_25_E,
    PRV_CPSS_TG_12_ETH_RES_26_E,
    PRV_CPSS_TG_12_ETH_RES_27_E,
    PRV_CPSS_TG_12_ETH_RES_28_E,
    PRV_CPSS_TG_12_ETH_RES_29_E,
    PRV_CPSS_TG_12_ETH_RES_30_E,
    PRV_CPSS_TG_12_ETH_RES_31_E,


    /* Lx Unit related interrupts           */
    /* Indexes 64 - 95                      */
    PRV_CPSS_TG_12_LX_RES_0_E,
    PRV_CPSS_TG_12_LX_LB_ERR_E,
    PRV_CPSS_TG_12_LX_RES_2_E,
    PRV_CPSS_TG_12_LX_RES_3_E,
    PRV_CPSS_TG_12_LX_RES_4_E,
    PRV_CPSS_TG_12_LX_RES_5_E,
    PRV_CPSS_TG_12_LX_RES_6_E,
    PRV_CPSS_TG_12_LX_TC_2_RF_CNTR_ALRM_E,
    PRV_CPSS_TG_12_LX_TC_2_RF_PLC_ALRM_E,
    PRV_CPSS_TG_12_LX_TC_2_RF_TBL_ERR_E,
    PRV_CPSS_TG_12_LX_CTRL_MEM_2_RF_ERR_E,
    PRV_CPSS_TG_12_LX_TCB_CNTR_E,
    PRV_CPSS_TG_12_LX_RES_12_E,
    PRV_CPSS_TG_12_LX_RES_13_E,
    PRV_CPSS_TG_12_LX_RES_14_E,
    PRV_CPSS_TG_12_LX_RES_15_E,
    PRV_CPSS_TG_12_LX_RES_16_E,
    PRV_CPSS_TG_12_LX_IPV4_LPM_ERR_0_E,
    PRV_CPSS_TG_12_LX_IPV4_LPM_ERR_1_E,
    PRV_CPSS_TG_12_LX_IPV4_LPM_ERR_2_E,
    PRV_CPSS_TG_12_LX_IPV4_LPM_ERR_3_E,
    PRV_CPSS_TG_12_LX_IPV4_LPM_ERR_4_E,
    PRV_CPSS_TG_12_LX_IPV4_ROUTE_ERR_E,
    PRV_CPSS_TG_12_LX_IPV4_CNTR_E,
    PRV_CPSS_TG_12_LX_IPV4_CNTR_SECOND_E,
    PRV_CPSS_TG_12_LX_RES_25_E,
    PRV_CPSS_TG_12_LX_RES_26_E,
    PRV_CPSS_TG_12_LX_RES_27_E,
    PRV_CPSS_TG_12_LX_TCAM_MISS0_E,
    PRV_CPSS_TG_12_LX_TCAM_MISS1_E,
    PRV_CPSS_TG_12_LX_TCAM_MISS2_E,
    PRV_CPSS_TG_12_LX_L3_L7_ERR_ADDR_E,


    /* Buffer Management related interrupts */
    /* Indexes 96 - 127                     */
    PRV_CPSS_TG_12_BM_RES_0_E,
    PRV_CPSS_TG_12_BM_MAX_BUFF_REACHED_PORT0_E,
    PRV_CPSS_TG_12_BM_MAX_BUFF_REACHED_PORT1_E,
    PRV_CPSS_TG_12_BM_MAX_BUFF_REACHED_PORT2_E,
    PRV_CPSS_TG_12_BM_MAX_BUFF_REACHED_PORT3_E,
    PRV_CPSS_TG_12_BM_MAX_BUFF_REACHED_PORT4_E,
    PRV_CPSS_TG_12_BM_MAX_BUFF_REACHED_PORT5_E,
    PRV_CPSS_TG_12_BM_MAX_BUFF_REACHED_PORT6_E,
    PRV_CPSS_TG_12_BM_MAX_BUFF_REACHED_PORT7_E,
    PRV_CPSS_TG_12_BM_MAX_BUFF_REACHED_PORT8_E,
    PRV_CPSS_TG_12_BM_MAX_BUFF_REACHED_PORT9_E,
    PRV_CPSS_TG_12_BM_MAX_BUFF_REACHED_PORT10_E,
    PRV_CPSS_TG_12_BM_MAX_BUFF_REACHED_PORT11_E,
    PRV_CPSS_TG_12_BM_RES_13_E,
    PRV_CPSS_TG_12_LOCAL_RXBUFF_FULL_E,
    PRV_CPSS_TG_12_BM_RES_15_E,
    PRV_CPSS_TG_12_BM_RES_16_E,
    PRV_CPSS_TG_12_BM_RES_17_E,
    PRV_CPSS_TG_12_BM_RES_18_E,
    PRV_CPSS_TG_12_BM_RES_19_E,
    PRV_CPSS_TG_12_BM_RES_20_E,
    PRV_CPSS_TG_12_BM_RES_21_E,
    PRV_CPSS_TG_12_BM_INVALID_ADDRESS_E,
    PRV_CPSS_TG_12_BM_RES_23_E,
    PRV_CPSS_TG_12_BM_RES_24_E,
    PRV_CPSS_TG_12_BM_RX_MEM_READ_ECC_ERROR_E,
    PRV_CPSS_TG_12_BM_RES_26_E,
    PRV_CPSS_TG_12_BM_VLT_ECC_ERR_E,
    PRV_CPSS_TG_12_BM_RES_28_E,
    PRV_CPSS_TG_12_BM_UPLINK_GPP_E,
    PRV_CPSS_TG_12_BM_RES_30_E,
    PRV_CPSS_TG_12_BM_RES_31_E,

    /* Buffer Management related interrupts */
    /* Cause 2                              */
    /* Indexes 128 - 159                    */
    PRV_CPSS_TG_12_BM2_RES_0_E,
    PRV_CPSS_TG_12_BM2_RES_1_E,
    PRV_CPSS_TG_12_BM2_RES_2_E,
    PRV_CPSS_TG_12_BM2_RES_3_E,
    PRV_CPSS_TG_12_BM2_RES_4_E,
    PRV_CPSS_TG_12_BM2_RES_5_E,
    PRV_CPSS_TG_12_BM2_RES_6_E,
    PRV_CPSS_TG_12_BM2_RES_7_E,
    PRV_CPSS_TG_12_BM2_RES_8_E,
    PRV_CPSS_TG_12_BM2_RES_9_E,
    PRV_CPSS_TG_12_BM_VLT_ECC_ERR_FIXED_INT_E,
    PRV_CPSS_TG_12_BM2_RES_11_E,
    PRV_CPSS_TG_12_BM2_RES_12_E,
    PRV_CPSS_TG_12_BM2_RES_13_E,
    PRV_CPSS_TG_12_BM2_RES_14_E,
    PRV_CPSS_TG_12_BM2_RES_15_E,
    PRV_CPSS_TG_12_BM2_RES_16_E,
    PRV_CPSS_TG_12_BM2_RES_17_E,
    PRV_CPSS_TG_12_BM2_RES_18_E,
    PRV_CPSS_TG_12_BM2_RES_19_E,
    PRV_CPSS_TG_12_BM2_RES_20_E,
    PRV_CPSS_TG_12_BM2_RES_21_E,
    PRV_CPSS_TG_12_BM2_RES_22_E,
    PRV_CPSS_TG_12_BM2_RES_23_E,
    PRV_CPSS_TG_12_BM2_RES_24_E,
    PRV_CPSS_TG_12_BM2_RES_25_E,
    PRV_CPSS_TG_12_BM2_RES_26_E,
    PRV_CPSS_TG_12_BM2_RES_27_E,
    PRV_CPSS_TG_12_BM2_RES_28_E,
    PRV_CPSS_TG_12_BM2_RES_29_E,
    PRV_CPSS_TG_12_BM2_RES_30_E,
    PRV_CPSS_TG_12_BM2_RES_31_E,


       /* MAC related interrupts               */
    /* Indexes 160 - 191                    */
    PRV_CPSS_TG_12_MAC0_RES_0_E,
    PRV_CPSS_TG_12_LINK_STATUS_CHANGED_PORT0_E,
    PRV_CPSS_TG_12_LINK_STATUS_CHANGED_PORT1_E,
    PRV_CPSS_TG_12_LINK_STATUS_CHANGED_PORT2_E,
    PRV_CPSS_TG_12_LINK_STATUS_CHANGED_PORT3_E,
    PRV_CPSS_TG_12_LINK_STATUS_CHANGED_PORT4_E,
    PRV_CPSS_TG_12_LINK_STATUS_CHANGED_PORT5_E,
    PRV_CPSS_TG_12_LINK_STATUS_CHANGED_PORT6_E,
    PRV_CPSS_TG_12_LINK_STATUS_CHANGED_PORT7_E,
    PRV_CPSS_TG_12_LINK_STATUS_CHANGED_PORT8_E,
    PRV_CPSS_TG_12_LINK_STATUS_CHANGED_PORT9_E,
    PRV_CPSS_TG_12_AN_COMPLETED_PORT0_E,
    PRV_CPSS_TG_12_AN_COMPLETED_PORT1_E,
    PRV_CPSS_TG_12_AN_COMPLETED_PORT2_E,
    PRV_CPSS_TG_12_AN_COMPLETED_PORT3_E,
    PRV_CPSS_TG_12_AN_COMPLETED_PORT4_E,
    PRV_CPSS_TG_12_AN_COMPLETED_PORT5_E,
    PRV_CPSS_TG_12_AN_COMPLETED_PORT6_E,
    PRV_CPSS_TG_12_AN_COMPLETED_PORT7_E,
    PRV_CPSS_TG_12_AN_COMPLETED_PORT8_E,
    PRV_CPSS_TG_12_AN_COMPLETED_PORT9_E,
    PRV_CPSS_TG_12_LINK_STATUS_CHANGED_PORT10_E,
    PRV_CPSS_TG_12_LINK_STATUS_CHANGED_PORT11_E,
    PRV_CPSS_TG_12_AN_COMPLETED_PORT10_E,
    PRV_CPSS_TG_12_AN_COMPLETED_PORT11_E,
    PRV_CPSS_TG_12_MAC0_RES_25_E,
    PRV_CPSS_TG_12_MAC0_RES_26_E,
    PRV_CPSS_TG_12_GPP_INTERRUPT1_E,
    PRV_CPSS_TG_12_GPP_INTERRUPT2_E,
    PRV_CPSS_TG_12_GPP_INTERRUPT3_E,
    PRV_CPSS_TG_12_MAC_MG_ADDR_OUT_OF_RANGE_E,
    PRV_CPSS_TG_12_COUNT_EXPIRED_E,


    /* Transmit Queues related interrupts   */
    /* Cause 0                              */
    /* Indexes 192 - 223                   */
    PRV_CPSS_TG_12_TXQ_RES_0_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT0_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT1_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT2_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT3_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT4_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT5_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT6_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT7_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT8_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT9_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT0_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT1_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT2_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT3_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT4_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT5_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT6_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT7_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT8_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT9_E,
    PRV_CPSS_TG_12_TQ_TXQ2_MG_FLUSH_E,
    PRV_CPSS_TG_12_TQ_LINK_LIST_ECC_ERR_HI_E,
    PRV_CPSS_TG_12_TQ_LINK_LIST_ECC_ERR_LO_E,
    PRV_CPSS_TG_12_TQ_MLL_PARITY_ERR_E,
    PRV_CPSS_TG_12_TQ_MG_READ_ERR_E,
    PRV_CPSS_TG_12_TXQ_RES_26_E,
    PRV_CPSS_TG_12_TXQ_RES_27_E,
    PRV_CPSS_TG_12_TXQ_RES_28_E,
    PRV_CPSS_TG_12_TXQ_RES_29_E,
    PRV_CPSS_TG_12_TXQ_RES_30_E,
    PRV_CPSS_TG_12_TXQ_RES_31_E,

    /* Cause 1                             */
    /* Indexes 224 - 255                   */
    PRV_CPSS_TG_12_TXQ1_RES_0_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT10_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT11_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT12_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT13_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT14_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT15_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT16_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT17_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT18_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT19_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT20_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT21_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT22_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT23_E,
    PRV_CPSS_TG_12_TQ_WATCHDOG_EX_PORT24_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT10_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT11_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT12_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT13_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT14_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT15_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT16_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT17_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT18_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT19_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT20_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT21_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT22_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT23_E,
    PRV_CPSS_TG_12_TQ_TXQ2_FLUSH_PORT24_E,
    PRV_CPSS_TG_12_TXQ1_RES_31_E,

    /* Cause 3                             */
    /* Indexes 256 - 287                   */
    PRV_CPSS_TG_12_TXQ3_RES_0_E,
    PRV_CPSS_TG_12_TXQ3_RES_1_E,
    PRV_CPSS_TG_12_TXQ3_RES_2_E,
    PRV_CPSS_TG_12_TXQ3_RES_3_E,
    PRV_CPSS_TG_12_TXQ3_RES_4_E,
    PRV_CPSS_TG_12_TXQ3_RES_5_E,
    PRV_CPSS_TG_12_TXQ3_RES_6_E,
    PRV_CPSS_TG_12_TXQ3_RES_7_E,
    PRV_CPSS_TG_12_TXQ3_RES_8_E,
    PRV_CPSS_TG_12_TXQ3_RES_9_E,
    PRV_CPSS_TG_12_TXQ3_RES_10_E,
    PRV_CPSS_TG_12_TXQ3_RES_11_E,
    PRV_CPSS_TG_12_TXQ3_RES_12_E,
    PRV_CPSS_TG_12_TXQ3_RES_13_E,
    PRV_CPSS_TG_12_TXQ3_RES_14_E,
    PRV_CPSS_TG_12_TXQ3_RES_15_E,
    PRV_CPSS_TG_12_TXQ3_RES_16_E,
    PRV_CPSS_TG_12_TXQ3_RES_17_E,
    PRV_CPSS_TG_12_TXQ3_RES_18_E,
    PRV_CPSS_TG_12_TXQ3_RES_19_E,
    PRV_CPSS_TG_12_TXQ3_RES_20_E,
    PRV_CPSS_TG_12_TXQ3_RES_21_E,
    PRV_CPSS_TG_12_TXQ3_RES_22_E,
    PRV_CPSS_TG_12_TXQ3_RES_23_E,
    PRV_CPSS_TG_12_TXQ3_RES_24_E,
    PRV_CPSS_TG_12_TXQ3_RES_25_E,
    PRV_CPSS_TG_12_TXQ3_RES_26_E,
    PRV_CPSS_TG_12_TQ_MC_FIFO_OVERRUN_E,
    PRV_CPSS_TG_12_TQ_TOTAL_DESC_UNDERFLOW_E,
    PRV_CPSS_TG_12_TQ_TOTAL_DESC_OVERFLOW_E,
    PRV_CPSS_TG_12_TQ_SNIFF_DESC_DROP_E,
    PRV_CPSS_TG_12_MC_FIFO_FULL_E,

    /* Cause 5                             */
    /* Indexes 288 - 319                    */
    PRV_CPSS_TG_12_TXQ5_RES_0_E,
    PRV_CPSS_TG_12_TXQ5_RES_1_E,
    PRV_CPSS_TG_12_TXQ5_RES_2_E,
    PRV_CPSS_TG_12_TXQ5_RES_3_E,
    PRV_CPSS_TG_12_TXQ5_RES_4_E,
    PRV_CPSS_TG_12_TXQ5_RES_5_E,
    PRV_CPSS_TG_12_TXQ5_RES_6_E,
    PRV_CPSS_TG_12_TXQ5_RES_7_E,
    PRV_CPSS_TG_12_TXQ5_RES_8_E,
    PRV_CPSS_TG_12_TXQ5_RES_9_E,
    PRV_CPSS_TG_12_TXQ5_RES_10_E,
    PRV_CPSS_TG_12_TXQ5_RES_11_E,
    PRV_CPSS_TG_12_TXQ5_RES_12_E,
    PRV_CPSS_TG_12_TXQ5_RES_13_E,
    PRV_CPSS_TG_12_TXQ5_RES_14_E,
    PRV_CPSS_TG_12_TXQ5_RES_15_E,
    PRV_CPSS_TG_12_TXQ5_RES_16_E,
    PRV_CPSS_TG_12_TXQ5_RES_17_E,
    PRV_CPSS_TG_12_TXQ5_RES_18_E,
    PRV_CPSS_TG_12_TXQ5_RES_19_E,
    PRV_CPSS_TG_12_TXQ5_RES_20_E,
    PRV_CPSS_TG_12_TXQ5_RES_21_E,
    PRV_CPSS_TG_12_TXQ5_RES_22_E,
    PRV_CPSS_TG_12_TQ_RED_REACHED_PORT_CPU_63_E,
    PRV_CPSS_TG_12_TXQ5_RES_24_E,
    PRV_CPSS_TG_12_TXQ5_RES_25_E,
    PRV_CPSS_TG_12_TXQ5_RES_26_E,
    PRV_CPSS_TG_12_TXQ5_RES_27_E,
    PRV_CPSS_TG_12_TXQ5_RES_28_E,
    PRV_CPSS_TG_12_TXQ5_RES_29_E,
    PRV_CPSS_TG_12_TXQ5_RES_30_E,
    PRV_CPSS_TG_12_TXQ5_RES_31_E,

    /* Miscellaneous interrupts             */
    /* Indexes 320 - 351                    */
    PRV_CPSS_TG_12_MISC_RES_0_E,
    PRV_CPSS_TG_12_MAC_AUQ_PENDING_E,
    PRV_CPSS_TG_12_EB_AUQ_FULL_E,
    PRV_CPSS_TG_12_MISC_RES_3_E,
    PRV_CPSS_TG_12_MISC_RES_4_E,
    PRV_CPSS_TG_12_MAC_AU_PROCESSED_E,
    PRV_CPSS_TG_12_MISC_C2C_W_FAR_END_UP_E,
    PRV_CPSS_TG_12_MISC_C2C_N_FAR_END_UP_E,
    PRV_CPSS_TG_12_MISC_C2C_DATA_ERR_E,
    PRV_CPSS_TG_12_MISC_MSG_TIME_OUT_E,
    PRV_CPSS_TG_12_MISC_ILLEGAL_ADDR_E,
    PRV_CPSS_TG_12_MISC_RES_11_E,
    PRV_CPSS_TG_12_MISC_RES_12_E,
    PRV_CPSS_TG_12_MISC_RES_13_E,
    PRV_CPSS_TG_12_MISC_RES_14_E,
    PRV_CPSS_TG_12_MISC_RES_15_E,
    PRV_CPSS_TG_12_MISC_RES_16_E,
    PRV_CPSS_TG_12_MISC_RES_17_E,
    PRV_CPSS_TG_12_MISC_RES_18_E,
    PRV_CPSS_TG_12_MISC_RES_19_E,
    PRV_CPSS_TG_12_MISC_RES_20_E,
    PRV_CPSS_TG_12_MISC_RES_21_E,
    PRV_CPSS_TG_12_MISC_RES_22_E,
    PRV_CPSS_TG_12_MISC_RES_23_E,
    PRV_CPSS_TG_12_MISC_RES_24_E,
    PRV_CPSS_TG_12_MISC_RES_25_E,
    PRV_CPSS_TG_12_MISC_RES_26_E,
    PRV_CPSS_TG_12_MISC_RES_27_E,
    PRV_CPSS_TG_12_MISC_RES_28_E,
    PRV_CPSS_TG_12_MISC_RES_29_E,
    PRV_CPSS_TG_12_MISC_RES_30_E,
    PRV_CPSS_TG_12_MISC_RES_31_E,


    /* Rx SDMA related interrupts           */
    /* Indexes 352 - 383                    */
    PRV_CPSS_TG_12_RX_RES_0_E,
    PRV_CPSS_TG_12_RX_RES_1_E,
    PRV_CPSS_TG_12_RX_BUFFER_QUEUE0_E,
    PRV_CPSS_TG_12_RX_BUFFER_QUEUE1_E,
    PRV_CPSS_TG_12_RX_BUFFER_QUEUE2_E,
    PRV_CPSS_TG_12_RX_BUFFER_QUEUE3_E,
    PRV_CPSS_TG_12_RX_BUFFER_QUEUE4_E,
    PRV_CPSS_TG_12_RX_BUFFER_QUEUE5_E,
    PRV_CPSS_TG_12_RX_BUFFER_QUEUE6_E,
    PRV_CPSS_TG_12_RX_BUFFER_QUEUE7_E,
    PRV_CPSS_TG_12_RX_RES_10_E,
    PRV_CPSS_TG_12_RX_ERR_QUEUE0_E,
    PRV_CPSS_TG_12_RX_ERR_QUEUE1_E,
    PRV_CPSS_TG_12_RX_ERR_QUEUE2_E,
    PRV_CPSS_TG_12_RX_ERR_QUEUE3_E,
    PRV_CPSS_TG_12_RX_ERR_QUEUE4_E,
    PRV_CPSS_TG_12_RX_ERR_QUEUE5_E,
    PRV_CPSS_TG_12_RX_ERR_QUEUE6_E,
    PRV_CPSS_TG_12_RX_ERR_QUEUE7_E,
    PRV_CPSS_TG_12_RX_RES_19_E,
    PRV_CPSS_TG_12_RX_RES_20_E,
    PRV_CPSS_TG_12_RX_RES_21_E,
    PRV_CPSS_TG_12_RX_RES_22_E,
    PRV_CPSS_TG_12_RX_RES_23_E,
    PRV_CPSS_TG_12_RX_RES_24_E,
    PRV_CPSS_TG_12_RX_RES_25_E,
    PRV_CPSS_TG_12_RX_RES_26_E,
    PRV_CPSS_TG_12_RX_RES_27_E,
    PRV_CPSS_TG_12_RX_RES_28_E,
    PRV_CPSS_TG_12_RX_RES_29_E,
    PRV_CPSS_TG_12_RX_RES_30_E,
    PRV_CPSS_TG_12_RX_RES_31_E,


    /* Tx SDMA related interrupts           */
    /* Indexes 384 - 415                     */
    PRV_CPSS_TG_12_TX_RES_0_E,
    PRV_CPSS_TG_12_TX_BUFFER_QUEUE0_E,
    PRV_CPSS_TG_12_TX_BUFFER_QUEUE1_E,
    PRV_CPSS_TG_12_TX_BUFFER_QUEUE2_E,
    PRV_CPSS_TG_12_TX_BUFFER_QUEUE3_E,
    PRV_CPSS_TG_12_TX_BUFFER_QUEUE4_E,
    PRV_CPSS_TG_12_TX_BUFFER_QUEUE5_E,
    PRV_CPSS_TG_12_TX_BUFFER_QUEUE6_E,
    PRV_CPSS_TG_12_TX_BUFFER_QUEUE7_E,
    PRV_CPSS_TG_12_TX_ERR_QUEUE0_E,
    PRV_CPSS_TG_12_TX_ERR_QUEUE1_E,
    PRV_CPSS_TG_12_TX_ERR_QUEUE2_E,
    PRV_CPSS_TG_12_TX_ERR_QUEUE3_E,
    PRV_CPSS_TG_12_TX_ERR_QUEUE4_E,
    PRV_CPSS_TG_12_TX_ERR_QUEUE5_E,
    PRV_CPSS_TG_12_TX_ERR_QUEUE6_E,
    PRV_CPSS_TG_12_TX_ERR_QUEUE7_E,
    PRV_CPSS_TG_12_TX_END_QUEUE0_E,
    PRV_CPSS_TG_12_TX_END_QUEUE1_E,
    PRV_CPSS_TG_12_TX_END_QUEUE2_E,
    PRV_CPSS_TG_12_TX_END_QUEUE3_E,
    PRV_CPSS_TG_12_TX_END_QUEUE4_E,
    PRV_CPSS_TG_12_TX_END_QUEUE5_E,
    PRV_CPSS_TG_12_TX_END_QUEUE6_E,
    PRV_CPSS_TG_12_TX_END_QUEUE7_E,
    PRV_CPSS_TG_12_TX_RES_25_E,
    PRV_CPSS_TG_12_TX_RES_26_E,
    PRV_CPSS_TG_12_TX_RES_27_E,
    PRV_CPSS_TG_12_TX_RES_28_E,
    PRV_CPSS_TG_12_TX_RES_29_E,
    PRV_CPSS_TG_12_TX_RES_30_E,
    PRV_CPSS_TG_12_TX_RES_31_E,

    /* MAC1 related interrupts.              */
    /* Indexes 416 - 447           */
    PRV_CPSS_TG_12_MAC1_RES_0_E,
    PRV_CPSS_TG_12_MAC1_RES_1_E,
    PRV_CPSS_TG_12_MAC1_RES_2_E,
    PRV_CPSS_TG_12_MAC1_RES_3_E,
    PRV_CPSS_TG_12_MAC1_RES_4_E,
    PRV_CPSS_TG_12_MAC1_RES_5_E,
    PRV_CPSS_TG_12_MAC1_RES_6_E,
    PRV_CPSS_TG_12_TX_FIFO_UNDERRUN_PORT0_E,
    PRV_CPSS_TG_12_TX_FIFO_UNDERRUN_PORT1_E,
    PRV_CPSS_TG_12_TX_FIFO_UNDERRUN_PORT2_E,
    PRV_CPSS_TG_12_TX_FIFO_UNDERRUN_PORT3_E,
    PRV_CPSS_TG_12_TX_FIFO_UNDERRUN_PORT4_E,
    PRV_CPSS_TG_12_TX_FIFO_UNDERRUN_PORT5_E,
    PRV_CPSS_TG_12_TX_FIFO_UNDERRUN_PORT6_E,
    PRV_CPSS_TG_12_TX_FIFO_UNDERRUN_PORT7_E,
    PRV_CPSS_TG_12_TX_FIFO_UNDERRUN_PORT8_E,
    PRV_CPSS_TG_12_TX_FIFO_UNDERRUN_PORT9_E,
    PRV_CPSS_TG_12_TX_FIFO_UNDERRUN_PORT10_E,
    PRV_CPSS_TG_12_TX_FIFO_UNDERRUN_PORT11_E,
    PRV_CPSS_TG_12_RX_FIFO_OVERRUN_PORT0_E,
    PRV_CPSS_TG_12_RX_FIFO_OVERRUN_PORT1_E,
    PRV_CPSS_TG_12_RX_FIFO_OVERRUN_PORT2_E,
    PRV_CPSS_TG_12_RX_FIFO_OVERRUN_PORT3_E,
    PRV_CPSS_TG_12_RX_FIFO_OVERRUN_PORT4_E,
    PRV_CPSS_TG_12_RX_FIFO_OVERRUN_PORT5_E,
    PRV_CPSS_TG_12_RX_FIFO_OVERRUN_PORT6_E,
    PRV_CPSS_TG_12_RX_FIFO_OVERRUN_PORT7_E,
    PRV_CPSS_TG_12_RX_FIFO_OVERRUN_PORT8_E,
    PRV_CPSS_TG_12_RX_FIFO_OVERRUN_PORT9_E,
    PRV_CPSS_TG_12_RX_FIFO_OVERRUN_PORT10_E,
    PRV_CPSS_TG_12_RX_FIFO_OVERRUN_PORT11_E,
    PRV_CPSS_TG_12_MAC1_RES_31_E,

    /* Indexes 448 - 479           */
    /* TXQ ExRMON Shadow Register Empty Interrupt Low ports 0-30 */
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_SUM_LOW_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT0_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT1_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT2_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT3_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT4_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT5_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT6_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT7_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT8_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT9_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT10_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT11_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT12_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT13_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT14_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT15_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT16_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT17_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT18_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT19_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT20_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT21_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT22_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT23_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT24_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT25_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT26_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT27_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT28_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT29_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT30_E,

    /* Indexes 480 - 511           */
    /* TXQ_EXRMON Shadow Register Empty Interrupt Low ports 31-51 */
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_SUM_HIGH_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT31_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT32_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT33_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT34_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT35_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT36_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT37_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT38_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT39_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT40_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT41_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT42_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT43_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT44_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT45_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT46_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT47_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT48_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT49_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT50_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT51_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_RES0_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_RES1_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_RES2_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_RES3_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_RES4_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_RES5_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_RES6_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_RES7_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_RES8_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_SHADOW_REG_EMPTY_RES9_E,


    /* Indexes 512 - 543           */
    /* TXQ_EXRMON Total Sample regs full Interrupt Low ports 0-30 */
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_SUM_LOW_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT0_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT1_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT2_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT3_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT4_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT5_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT6_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT7_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT8_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT9_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT10_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT11_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT12_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT13_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT14_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT15_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT16_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT17_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT18_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT19_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT20_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT21_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT22_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT23_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT24_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT25_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT26_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT27_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT28_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT29_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT30_E,

    /* Indexes 544 - 575           */
    /* TXQ EXRMON Total Sample regs full Interrupt Low ports 31-51 */
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_SUM_HIGH_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT31_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT32_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT33_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT34_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT35_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT36_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT37_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT38_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT39_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT40_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT41_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT42_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT43_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT44_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT45_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT46_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT47_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT48_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT49_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT50_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT51_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_RES0_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_RES1_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_RES2_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_RES3_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_RES4_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_RES5_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_RES6_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_RES7_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_RES8_E,
    PRV_CPSS_TG_12_TXQ_EXRMON_TOTAL_SAMP_FULL_RES9_E,

    /* Indexes 576 - 607           */
    /* EPF ExRMON Shadow Register Empty Interrupt Low ports 0-30 */
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_SUM_LOW_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT0_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT1_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT2_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT3_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT4_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT5_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT6_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT7_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT8_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT9_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT10_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT11_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT12_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT13_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT14_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT15_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT16_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT17_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT18_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT19_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT20_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT21_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT22_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT23_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT24_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT25_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT26_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT27_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT28_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT29_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT30_E,

    /* Indexes 608 - 639           */
    /* EPF ExRMON Shadow Register Empty Interrupt Low ports 31-51 */
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_SUM_HIGH_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT31_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT32_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT33_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT34_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT35_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT36_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT37_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT38_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT39_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT40_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT41_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT42_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT43_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT44_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT45_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT46_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT47_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT48_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT49_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT50_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_PORT51_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_RES0_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_RES1_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_RES2_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_RES3_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_RES4_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_RES5_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_RES6_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_RES7_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_RES8_E,
    PRV_CPSS_TG_12_EPF_EXRMON_SHADOW_REG_EMPTY_RES9_E,


    /* Indexes 640 - 671           */
    /* EPF ExRMON Total Samp full Interrupt Low ports 0-30 */
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_SUM_LOW_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT0_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT1_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT2_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT3_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT4_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT5_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT6_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT7_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT8_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT9_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT10_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT11_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT12_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT13_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT14_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT15_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT16_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT17_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT18_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT19_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT20_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT21_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT22_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT23_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT24_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT25_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT26_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT27_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT28_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT29_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT30_E,

    /* Indexes 672 - 703           */
    /* EPF EXRMON Total Samp full Interrupt Low ports 31-51 */
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_SUM_HIGH_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT31_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT32_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT33_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT34_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT35_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT36_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT37_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT38_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT39_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT40_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT41_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT42_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT43_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT44_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT45_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT46_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT47_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT48_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT49_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT50_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_PORT51_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_RES0_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_RES1_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_RES2_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_RES3_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_RES4_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_RES5_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_RES6_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_RES7_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_RES8_E,
    PRV_CPSS_TG_12_EPF_EXRMON_TOTAL_SAMP_FULL_RES9_E,

    PRV_CPSS_TG_12_LAST_INT         /* should be always last in enum */

}PRV_CPSS_TG_12_INT_CAUSE_ENT;

/*
 * Typedef: enum PRV_CPSS_TG_52_INT_CAUSE
 *
 * Description: All interrupt cause indexes_E, to be used for interrupts handling_E,
 *              and parameters change.
 *
 * NOTE : If needed_E, new interrupt bits can replace the XXX_RES_i bits_E, in case
 *        that these bits fall into the same cause registers.
 *
 *       Applicable devices: Tiger
 *                           52 ports - 98EX116 , 98EX106 , 98EX108 , 98EX116DI
 *
 * Comment:
 *      Please see the description of each of the following interrupt event
 *      cause registers in the packet processor datasheet.
 */
typedef enum
{
    /* Summary and PCI interrupts   */
    /* Indexes 0 - 31               */
    PRV_CPSS_TG_52_SUM_RES_0_E               = 0,
    PRV_CPSS_TG_52_MAS_READ_ERR_E,
    PRV_CPSS_TG_52_SLV_WRITE_ERR_E,
    PRV_CPSS_TG_52_MAS_WRITE_ERR_E,
    PRV_CPSS_TG_52_ADDR_ERR_E,
    PRV_CPSS_TG_52_MAS_ABORT_E,
    PRV_CPSS_TG_52_TARGET_ABORT_E,
    PRV_CPSS_TG_52_SLV_READ_ERR_E,
    PRV_CPSS_TG_52_RETRY_CNTR_E,
    PRV_CPSS_TG_52_SUM_RES_9_E,
    PRV_CPSS_TG_52_SUM_RES_10_E,
    PRV_CPSS_TG_52_SUM_RES_11_E,
    PRV_CPSS_TG_52_SUM_RES_12_E,
    PRV_CPSS_TG_52_SUM_RES_13_E,
    PRV_CPSS_TG_52_SUM_RES_14_E,
    PRV_CPSS_TG_52_SUM_RES_15_E,
    PRV_CPSS_TG_52_SUM_RES_16_E,
    PRV_CPSS_TG_52_SUM_RES_17_E,
    PRV_CPSS_TG_52_SUM_RES_18_E,
    PRV_CPSS_TG_52_SUM_RES_19_E,
    PRV_CPSS_TG_52_SUM_RES_20_E,
    PRV_CPSS_TG_52_SUM_RES_21_E,
    PRV_CPSS_TG_52_SUM_RES_22_E,
    PRV_CPSS_TG_52_SUM_RES_23_E,
    PRV_CPSS_TG_52_SUM_RES_24_E,
    PRV_CPSS_TG_52_SUM_RES_25_E,
    PRV_CPSS_TG_52_SUM_RES_26_E,
    PRV_CPSS_TG_52_SUM_RES_27_E,
    PRV_CPSS_TG_52_SUM_RES_28_E,
    PRV_CPSS_TG_52_SUM_RES_29_E,
    PRV_CPSS_TG_52_SUM_RES_30_E,
    PRV_CPSS_TG_52_SUM_RES_31_E,

    /* Ethernet Bridge interrupts   */
    /* Indexes 32 - 63              */
    PRV_CPSS_TG_52_ETH_RES_0_E,
    PRV_CPSS_TG_52_EB_NA_FIFO_FULL_E,
    PRV_CPSS_TG_52_MAC_NUM_OF_HOP_EXP_E,
    PRV_CPSS_TG_52_MAC_AGE_VIA_TRIGGER_ENDED_E,
    PRV_CPSS_TG_52_MAC_NA_LEARNED_E,
    PRV_CPSS_TG_52_MAC_NA_NOT_LEARNED_E,
    PRV_CPSS_TG_52_MAC_TBL_READ_ECC_ERR_E,
    PRV_CPSS_TG_52_EB_MG_ADDR_OUT_OF_RANGE_E,
    PRV_CPSS_TG_52_EB_INGRESS_FILTER_PCKT_E,
    PRV_CPSS_TG_52_EB_NA_NOT_LEARNED_SECURITY_BREACH_E,
    PRV_CPSS_TG_52_ETH_RES_10_E,
    PRV_CPSS_TG_52_ETH_RES_11_E,
    PRV_CPSS_TG_52_ETH_RES_12_E,
    PRV_CPSS_TG_52_ETH_RES_13_E,
    PRV_CPSS_TG_52_ETH_RES_14_E,
    PRV_CPSS_TG_52_ETH_RES_15_E,
    PRV_CPSS_TG_52_ETH_RES_16_E,
    PRV_CPSS_TG_52_ETH_RES_17_E,
    PRV_CPSS_TG_52_ETH_RES_18_E,
    PRV_CPSS_TG_52_ETH_RES_19_E,
    PRV_CPSS_TG_52_ETH_RES_20_E,
    PRV_CPSS_TG_52_ETH_RES_21_E,
    PRV_CPSS_TG_52_ETH_RES_22_E,
    PRV_CPSS_TG_52_ETH_RES_23_E,
    PRV_CPSS_TG_52_ETH_RES_24_E,
    PRV_CPSS_TG_52_ETH_RES_25_E,
    PRV_CPSS_TG_52_ETH_RES_26_E,
    PRV_CPSS_TG_52_ETH_RES_27_E,
    PRV_CPSS_TG_52_ETH_RES_28_E,
    PRV_CPSS_TG_52_ETH_RES_29_E,
    PRV_CPSS_TG_52_ETH_RES_30_E,
    PRV_CPSS_TG_52_ETH_RES_31_E,


    /* Lx Unit related interrupts           */
    /* Indexes 64 - 95                      */
    PRV_CPSS_TG_52_LX_RES_0_E,
    PRV_CPSS_TG_52_LX_LB_ERR_E,
    PRV_CPSS_TG_52_LX_RES_2_E,
    PRV_CPSS_TG_52_LX_RES_3_E,
    PRV_CPSS_TG_52_LX_RES_4_E,
    PRV_CPSS_TG_52_LX_RES_5_E,
    PRV_CPSS_TG_52_LX_RES_6_E,
    PRV_CPSS_TG_52_LX_TC_2_RF_CNTR_ALRM_E,
    PRV_CPSS_TG_52_LX_TC_2_RF_PLC_ALRM_E,
    PRV_CPSS_TG_52_LX_TC_2_RF_TBL_ERR_E,
    PRV_CPSS_TG_52_LX_CTRL_MEM_2_RF_ERR_E,
    PRV_CPSS_TG_52_LX_TCB_CNTR_E,
    PRV_CPSS_TG_52_LX_RES_12_E,
    PRV_CPSS_TG_52_LX_RES_13_E,
    PRV_CPSS_TG_52_LX_RES_14_E,
    PRV_CPSS_TG_52_LX_RES_15_E,
    PRV_CPSS_TG_52_LX_RES_16_E,
    PRV_CPSS_TG_52_LX_IPV4_LPM_ERR_0_E,
    PRV_CPSS_TG_52_LX_IPV4_LPM_ERR_1_E,
    PRV_CPSS_TG_52_LX_IPV4_LPM_ERR_2_E,
    PRV_CPSS_TG_52_LX_IPV4_LPM_ERR_3_E,
    PRV_CPSS_TG_52_LX_IPV4_LPM_ERR_4_E,
    PRV_CPSS_TG_52_LX_IPV4_ROUTE_ERR_E,
    PRV_CPSS_TG_52_LX_IPV4_CNTR_E,
    PRV_CPSS_TG_52_LX_IPV4_CNTR_SECOND_E,
    PRV_CPSS_TG_52_LX_RES_25_E,
    PRV_CPSS_TG_52_LX_RES_26_E,
    PRV_CPSS_TG_52_LX_RES_27_E,
    PRV_CPSS_TG_52_LX_TCAM_MISS0_E,
    PRV_CPSS_TG_52_LX_TCAM_MISS1_E,
    PRV_CPSS_TG_52_LX_TCAM_MISS2_E,
    PRV_CPSS_TG_52_LX_L3_L7_ERR_ADDR_E,


    /* Buffer Management related interrupts */
    /* Indexes 96 - 127                     */
    PRV_CPSS_TG_52_BM_RES_0_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT0_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT1_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT2_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT3_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT4_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT5_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT6_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT7_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT8_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT9_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT10_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT11_E,
    PRV_CPSS_TG_52_BM_RES_13_E,
    PRV_CPSS_TG_52_LOCAL_RXBUFF_FULL_E,
    PRV_CPSS_TG_52_BM_RES_15_E,
    PRV_CPSS_TG_52_BM_RES_16_E,
    PRV_CPSS_TG_52_BM_RES_17_E,
    PRV_CPSS_TG_52_BM_RES_18_E,
    PRV_CPSS_TG_52_BM_RES_19_E,
    PRV_CPSS_TG_52_BM_RES_20_E,
    PRV_CPSS_TG_52_BM_RES_21_E,
    PRV_CPSS_TG_52_BM_INVALID_ADDRESS_E,
    PRV_CPSS_TG_52_BM_RES_23_E,
    PRV_CPSS_TG_52_BM_RES_24_E,
    PRV_CPSS_TG_52_BM_RX_MEM_READ_ECC_ERROR_E,
    PRV_CPSS_TG_52_BM_RES_26_E,
    PRV_CPSS_TG_52_BM_VLT_ECC_ERR_E,
    PRV_CPSS_TG_52_BM_RES_28_E,
    PRV_CPSS_TG_52_BM_UPLINK_GPP_E,
    PRV_CPSS_TG_52_BM_RES_30_E,
    PRV_CPSS_TG_52_BM_RES_31_E,

    /* Buffer Management related interrupts */
    /* Cause 1                              */
    /* Indexes 128 - 159                    */
    PRV_CPSS_TG_52_BM1_RES_0_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT12_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT13_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT14_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT15_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT16_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT17_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT18_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT19_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT20_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT21_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT22_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT23_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT24_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT25_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT26_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT27_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT28_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT29_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT30_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT31_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT32_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT33_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT34_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT35_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT36_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT37_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT38_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT39_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT40_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT41_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT42_E,

    /* Buffer Management related interrupts */
    /* Cause 2                              */
    /* Indexes 160 - 191                    */
    PRV_CPSS_TG_52_BM2_RES_0_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT43_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT44_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT45_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT46_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT47_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT48_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT49_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT50_E,
    PRV_CPSS_TG_52_BM_MAX_BUFF_REACHED_PORT51_E,
    PRV_CPSS_TG_52_BM_VLT_ECC_ERR_FIXED_INT_E,
   /* PRV_CPSS_TG_52_BM2_RES_10_E,*/
    PRV_CPSS_TG_52_BM2_RES_11_E,
    PRV_CPSS_TG_52_BM2_RES_12_E,
    PRV_CPSS_TG_52_BM2_RES_13_E,
    PRV_CPSS_TG_52_BM2_RES_14_E,
    PRV_CPSS_TG_52_BM2_RES_15_E,
    PRV_CPSS_TG_52_BM2_RES_16_E,
    PRV_CPSS_TG_52_BM2_RES_17_E,
    PRV_CPSS_TG_52_BM2_RES_18_E,
    PRV_CPSS_TG_52_BM2_RES_19_E,
    PRV_CPSS_TG_52_BM2_RES_20_E,
    PRV_CPSS_TG_52_BM2_RES_21_E,
    PRV_CPSS_TG_52_BM2_RES_22_E,
    PRV_CPSS_TG_52_BM2_RES_23_E,
    PRV_CPSS_TG_52_BM2_RES_24_E,
    PRV_CPSS_TG_52_BM2_RES_25_E,
    PRV_CPSS_TG_52_BM2_RES_26_E,
    PRV_CPSS_TG_52_BM2_RES_27_E,
    PRV_CPSS_TG_52_BM2_RES_28_E,
    PRV_CPSS_TG_52_BM2_RES_29_E,
    PRV_CPSS_TG_52_BM2_RES_30_E,
    PRV_CPSS_TG_52_BM2_RES_31_E,


    /* MAC related interrupts               */
    /* GOP 0                                */
    /* Indexes 192 - 223                    */
    PRV_CPSS_TG_52_MAC0_RES_0_E,
    PRV_CPSS_TG_52_MAC0_RES_1_E,
    PRV_CPSS_TG_52_MAC0_RES_2_E,
    PRV_CPSS_TG_52_MAC0_RES_3_E,
    PRV_CPSS_TG_52_MAC0_RES_4_E,
    PRV_CPSS_TG_52_MAC0_RES_5_E,
    PRV_CPSS_TG_52_MAC0_RES_6_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT48_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT49_E,
    PRV_CPSS_TG_52_MAC0_RES_9_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT50_E,
    PRV_CPSS_TG_52_MAC0_RES_11_E,
    PRV_CPSS_TG_52_MAC0_RES_12_E,
    PRV_CPSS_TG_52_MAC0_RES_13_E,
    PRV_CPSS_TG_52_MAC0_RES_14_E,
    PRV_CPSS_TG_52_MAC0_RES_15_E,
    PRV_CPSS_TG_52_MAC0_RES_16_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT48_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT49_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT50_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT51_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT51_E,
    PRV_CPSS_TG_52_MAC0_RES_22_E,
    PRV_CPSS_TG_52_MAC0_RES_23_E,
    PRV_CPSS_TG_52_MAC0_RES_24_E,
    PRV_CPSS_TG_52_MAC0_RES_25_E,
    PRV_CPSS_TG_52_MAC0_RES_26_E,
    PRV_CPSS_TG_52_GPP_INTERRUPT1_E,
    PRV_CPSS_TG_52_GPP_INTERRUPT2_E,
    PRV_CPSS_TG_52_GPP_INTERRUPT3_E,
    PRV_CPSS_TG_52_MAC_MG_ADDR_OUT_OF_RANGE_E,
    PRV_CPSS_TG_52_COUNT_EXPIRED_E,

    /* GOP 1                                */
    /* Indexes 224 - 255                    */
    PRV_CPSS_TG_52_MAC2_GOP1_RES_0_E,
    PRV_CPSS_TG_52_MAC2_GOP1_RES_1_E,
    PRV_CPSS_TG_52_MAC2_GOP1_RES_2_E,
    PRV_CPSS_TG_52_MAC2_GOP1_RES_3_E,
    PRV_CPSS_TG_52_MAC2_GOP1_RES_4_E,
    PRV_CPSS_TG_52_MAC2_GOP1_RES_5_E,
    PRV_CPSS_TG_52_MAC2_GOP1_RES_6_E,
    PRV_CPSS_TG_52_MAC2_GOP1_RES_7_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT0_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT1_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT2_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT3_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT4_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT5_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT6_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT7_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT8_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT9_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT10_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT11_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT0_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT1_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT2_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT3_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT4_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT5_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT6_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT7_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT8_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT9_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT10_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT11_E,

    /* GOP 2                                */
    /* Indexes 256 - 287                    */
    PRV_CPSS_TG_52_MAC2_GOP2_RES_0_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT12_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT13_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT14_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT15_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT16_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT17_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT18_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT19_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT20_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT21_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT22_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT23_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT12_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT13_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT14_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT15_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT16_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT17_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT18_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT19_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT20_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT21_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT22_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT23_E,
    PRV_CPSS_TG_52_MAC2_GOP2_RES_25_E,
    PRV_CPSS_TG_52_MAC2_GOP2_RES_26_E,
    PRV_CPSS_TG_52_MAC2_GOP2_RES_27_E,
    PRV_CPSS_TG_52_MAC2_GOP2_RES_28_E,
    PRV_CPSS_TG_52_MAC2_GOP2_RES_29_E,
    PRV_CPSS_TG_52_MAC2_GOP2_RES_30_E,
    PRV_CPSS_TG_52_MAC2_GOP2_RES_31_E,

    /* GOP 3                                */
    /* Indexes 288 - 319                    */
    PRV_CPSS_TG_52_MAC2_GOP3_RES_0_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT24_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT25_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT26_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT27_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT28_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT29_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT30_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT31_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT32_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT33_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT34_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT35_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT24_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT25_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT26_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT27_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT28_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT29_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT30_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT31_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT32_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT33_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT34_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT35_E,
    PRV_CPSS_TG_52_MAC2_GOP3_RES_25_E,
    PRV_CPSS_TG_52_MAC2_GOP3_RES_26_E,
    PRV_CPSS_TG_52_MAC2_GOP3_RES_27_E,
    PRV_CPSS_TG_52_MAC2_GOP3_RES_28_E,
    PRV_CPSS_TG_52_MAC2_GOP3_RES_29_E,
    PRV_CPSS_TG_52_MAC2_GOP3_RES_30_E,
    PRV_CPSS_TG_52_MAC2_GOP3_RES_31_E,

    /* GOP 4                                */
    /* Indexes 320 - 351                    */
    PRV_CPSS_TG_52_MAC2_GOP4_RES_0_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT36_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT37_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT38_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT39_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT40_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT41_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT42_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT43_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT44_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT45_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT46_E,
    PRV_CPSS_TG_52_LINK_STATUS_CHANGED_PORT47_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT36_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT37_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT38_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT39_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT40_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT41_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT42_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT43_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT44_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT45_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT46_E,
    PRV_CPSS_TG_52_AN_COMPLETED_PORT47_E,
    PRV_CPSS_TG_52_MAC2_GOP4_RES_25_E,
    PRV_CPSS_TG_52_MAC2_GOP4_RES_26_E,
    PRV_CPSS_TG_52_MAC2_GOP4_RES_27_E,
    PRV_CPSS_TG_52_MAC2_GOP4_RES_28_E,
    PRV_CPSS_TG_52_MAC2_GOP4_RES_29_E,
    PRV_CPSS_TG_52_MAC2_GOP4_RES_30_E,
    PRV_CPSS_TG_52_MAC2_GOP4_RES_31_E,


    /* Transmit Queues related interrupts   */
    /* Cause 0                              */
    /* Indexes 352 - 383                    */
    PRV_CPSS_TG_52_TXQ_RES_0_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT0_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT1_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT2_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT3_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT4_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT5_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT6_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT7_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT8_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT9_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT0_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT1_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT2_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT3_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT4_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT5_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT6_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT7_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT8_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT9_E,
    PRV_CPSS_TG_52_TQ_TXQ2_MG_FLUSH_E,
    PRV_CPSS_TG_52_TQ_LINK_LIST_ECC_ERR_HI_E,
    PRV_CPSS_TG_52_TQ_LINK_LIST_ECC_ERR_LO_E,
    PRV_CPSS_TG_52_TQ_MLL_PARITY_ERR_E,
    PRV_CPSS_TG_52_TQ_MG_READ_ERR_E,
    PRV_CPSS_TG_52_TXQ_RES_26_E,
    PRV_CPSS_TG_52_TXQ_RES_27_E,
    PRV_CPSS_TG_52_TXQ_RES_28_E,
    PRV_CPSS_TG_52_TXQ_RES_29_E,
    PRV_CPSS_TG_52_TXQ_RES_30_E,
    PRV_CPSS_TG_52_TXQ_RES_31_E,

    /* Cause 1                             */
    /* Indexes 384 - 415                   */
    PRV_CPSS_TG_52_TXQ1_RES_0_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT10_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT11_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT12_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT13_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT14_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT15_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT16_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT17_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT18_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT19_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT20_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT21_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT22_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT23_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT24_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT10_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT11_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT12_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT13_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT14_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT15_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT16_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT17_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT18_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT19_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT20_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT21_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT22_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT23_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT24_E,
    PRV_CPSS_TG_52_TXQ1_RES_31_E,

    /* Cause 2                             */
    /* Indexes 416 - 447                   */
    PRV_CPSS_TG_52_TXQ2_RES_0_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT25_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT26_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT27_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT28_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT29_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT30_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT31_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT32_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT33_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT34_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT35_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT36_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT37_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT38_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT39_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT25_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT26_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT27_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT28_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT29_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT30_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT31_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT32_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT33_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT34_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT35_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT36_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT37_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT38_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT39_E,
    PRV_CPSS_TG_52_TXQ2_RES_31_E,

    /* Cause 3                             */
    /* Indexes 448 - 479                   */
    PRV_CPSS_TG_52_TXQ3_RES_0_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT40_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT41_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT42_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT43_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT44_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT45_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT46_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT47_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT48_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT49_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT50_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT51_E,
    PRV_CPSS_TG_52_TQ_WATCHDOG_EX_PORT52_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT40_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT41_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT42_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT43_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT44_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT45_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT46_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT47_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT48_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT49_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT50_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT51_E,
    PRV_CPSS_TG_52_TQ_TXQ2_FLUSH_PORT52_E,
    PRV_CPSS_TG_52_TQ_MC_FIFO_OVERRUN_E,
    PRV_CPSS_TG_52_TQ_TOTAL_DESC_UNDERFLOW_E,
    PRV_CPSS_TG_52_TQ_TOTAL_DESC_OVERFLOW_E,
    PRV_CPSS_TG_52_TQ_SNIFF_DESC_DROP_E,
    PRV_CPSS_TG_52_MC_FIFO_FULL_E,

    /* Cause 4                             */
    /* Indexes 480 - 511                   */
    PRV_CPSS_TG_52_TXQ4_RES_0_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT0_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT1_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT2_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT3_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT4_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT5_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT6_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT7_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT8_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT9_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT10_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT11_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT12_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT13_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT14_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT15_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT16_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT17_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT18_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT19_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT20_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT21_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT22_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT23_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT24_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT25_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT26_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT27_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT28_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT29_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT30_E,

    /* Cause 5                             */
    /* Indexes 512 - 543                   */
    PRV_CPSS_TG_52_TXQ5_RES_0_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT31_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT32_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT33_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT34_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT35_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT36_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT37_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT38_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT39_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT40_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT41_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT42_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT43_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT44_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT45_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT46_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT47_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT48_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT49_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT50_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT51_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT52_E,
    PRV_CPSS_TG_52_TQ_RED_REACHED_PORT_CPU_63_E,
    PRV_CPSS_TG_52_TXQ5_RES_24_E,
    PRV_CPSS_TG_52_TXQ5_RES_25_E,
    PRV_CPSS_TG_52_TXQ5_RES_26_E,
    PRV_CPSS_TG_52_TXQ5_RES_27_E,
    PRV_CPSS_TG_52_TXQ5_RES_28_E,
    PRV_CPSS_TG_52_TXQ5_RES_29_E,
    PRV_CPSS_TG_52_TXQ5_RES_30_E,
    PRV_CPSS_TG_52_TXQ5_RES_31_E,

    /* Miscellaneous interrupts             */
    /* Indexes 544 - 575                    */
    PRV_CPSS_TG_52_MISC_RES_0_E,
    PRV_CPSS_TG_52_MAC_AUQ_PENDING_E,
    PRV_CPSS_TG_52_EB_AUQ_FULL_E,
    PRV_CPSS_TG_52_MISC_RES_3_E,
    PRV_CPSS_TG_52_MISC_RES_4_E,
    PRV_CPSS_TG_52_MAC_AU_PROCESSED_E,
    PRV_CPSS_TG_52_MISC_C2C_W_FAR_END_UP_E,
    PRV_CPSS_TG_52_MISC_C2C_N_FAR_END_UP_E,
    PRV_CPSS_TG_52_MISC_C2C_DATA_ERR_E,
    PRV_CPSS_TG_52_MISC_MSG_TIME_OUT_E,
    PRV_CPSS_TG_52_MISC_ILLEGAL_ADDR_E,
    PRV_CPSS_TG_52_MISC_RES_11_E,
    PRV_CPSS_TG_52_MISC_RES_12_E,
    PRV_CPSS_TG_52_MISC_RES_13_E,
    PRV_CPSS_TG_52_MISC_RES_14_E,
    PRV_CPSS_TG_52_MISC_RES_15_E,
    PRV_CPSS_TG_52_MISC_RES_16_E,
    PRV_CPSS_TG_52_MISC_RES_17_E,
    PRV_CPSS_TG_52_MISC_RES_18_E,
    PRV_CPSS_TG_52_MISC_RES_19_E,
    PRV_CPSS_TG_52_MISC_RES_20_E,
    PRV_CPSS_TG_52_MISC_RES_21_E,
    PRV_CPSS_TG_52_MISC_RES_22_E,
    PRV_CPSS_TG_52_MISC_RES_23_E,
    PRV_CPSS_TG_52_MISC_RES_24_E,
    PRV_CPSS_TG_52_MISC_RES_25_E,
    PRV_CPSS_TG_52_MISC_RES_26_E,
    PRV_CPSS_TG_52_MISC_RES_27_E,
    PRV_CPSS_TG_52_MISC_RES_28_E,
    PRV_CPSS_TG_52_MISC_RES_29_E,
    PRV_CPSS_TG_52_MISC_RES_30_E,
    PRV_CPSS_TG_52_MISC_RES_31_E,


    /* Rx SDMA related interrupts           */
    /* Indexes 576 - 607                    */
    PRV_CPSS_TG_52_RX_RES_0_E,
    PRV_CPSS_TG_52_RX_RES_1_E,
    PRV_CPSS_TG_52_RX_BUFFER_QUEUE0_E,
    PRV_CPSS_TG_52_RX_BUFFER_QUEUE1_E,
    PRV_CPSS_TG_52_RX_BUFFER_QUEUE2_E,
    PRV_CPSS_TG_52_RX_BUFFER_QUEUE3_E,
    PRV_CPSS_TG_52_RX_BUFFER_QUEUE4_E,
    PRV_CPSS_TG_52_RX_BUFFER_QUEUE5_E,
    PRV_CPSS_TG_52_RX_BUFFER_QUEUE6_E,
    PRV_CPSS_TG_52_RX_BUFFER_QUEUE7_E,
    PRV_CPSS_TG_52_RX_RES_10_E,
    PRV_CPSS_TG_52_RX_ERR_QUEUE0_E,
    PRV_CPSS_TG_52_RX_ERR_QUEUE1_E,
    PRV_CPSS_TG_52_RX_ERR_QUEUE2_E,
    PRV_CPSS_TG_52_RX_ERR_QUEUE3_E,
    PRV_CPSS_TG_52_RX_ERR_QUEUE4_E,
    PRV_CPSS_TG_52_RX_ERR_QUEUE5_E,
    PRV_CPSS_TG_52_RX_ERR_QUEUE6_E,
    PRV_CPSS_TG_52_RX_ERR_QUEUE7_E,
    PRV_CPSS_TG_52_RX_RES_19_E,
    PRV_CPSS_TG_52_RX_RES_20_E,
    PRV_CPSS_TG_52_RX_RES_21_E,
    PRV_CPSS_TG_52_RX_RES_22_E,
    PRV_CPSS_TG_52_RX_RES_23_E,
    PRV_CPSS_TG_52_RX_RES_24_E,
    PRV_CPSS_TG_52_RX_RES_25_E,
    PRV_CPSS_TG_52_RX_RES_26_E,
    PRV_CPSS_TG_52_RX_RES_27_E,
    PRV_CPSS_TG_52_RX_RES_28_E,
    PRV_CPSS_TG_52_RX_RES_29_E,
    PRV_CPSS_TG_52_RX_RES_30_E,
    PRV_CPSS_TG_52_RX_RES_31_E,


    /* Tx SDMA related interrupts           */
    /* Indexes 608 - 639                    */
    PRV_CPSS_TG_52_TX_RES_0_E,
    PRV_CPSS_TG_52_TX_BUFFER_QUEUE0_E,
    PRV_CPSS_TG_52_TX_BUFFER_QUEUE1_E,
    PRV_CPSS_TG_52_TX_BUFFER_QUEUE2_E,
    PRV_CPSS_TG_52_TX_BUFFER_QUEUE3_E,
    PRV_CPSS_TG_52_TX_BUFFER_QUEUE4_E,
    PRV_CPSS_TG_52_TX_BUFFER_QUEUE5_E,
    PRV_CPSS_TG_52_TX_BUFFER_QUEUE6_E,
    PRV_CPSS_TG_52_TX_BUFFER_QUEUE7_E,
    PRV_CPSS_TG_52_TX_ERR_QUEUE0_E,
    PRV_CPSS_TG_52_TX_ERR_QUEUE1_E,
    PRV_CPSS_TG_52_TX_ERR_QUEUE2_E,
    PRV_CPSS_TG_52_TX_ERR_QUEUE3_E,
    PRV_CPSS_TG_52_TX_ERR_QUEUE4_E,
    PRV_CPSS_TG_52_TX_ERR_QUEUE5_E,
    PRV_CPSS_TG_52_TX_ERR_QUEUE6_E,
    PRV_CPSS_TG_52_TX_ERR_QUEUE7_E,
    PRV_CPSS_TG_52_TX_END_QUEUE0_E,
    PRV_CPSS_TG_52_TX_END_QUEUE1_E,
    PRV_CPSS_TG_52_TX_END_QUEUE2_E,
    PRV_CPSS_TG_52_TX_END_QUEUE3_E,
    PRV_CPSS_TG_52_TX_END_QUEUE4_E,
    PRV_CPSS_TG_52_TX_END_QUEUE5_E,
    PRV_CPSS_TG_52_TX_END_QUEUE6_E,
    PRV_CPSS_TG_52_TX_END_QUEUE7_E,
    PRV_CPSS_TG_52_TX_RES_25_E,
    PRV_CPSS_TG_52_TX_RES_26_E,
    PRV_CPSS_TG_52_TX_RES_27_E,
    PRV_CPSS_TG_52_TX_RES_28_E,
    PRV_CPSS_TG_52_TX_RES_29_E,
    PRV_CPSS_TG_52_TX_RES_30_E,
    PRV_CPSS_TG_52_TX_RES_31_E,

    /* MAC1 related interrupts.             */
    /* GOP 5                                */
    /* Indexes 640 - 671                    */
    PRV_CPSS_TG_52_MAC1_RES_0_E,
    PRV_CPSS_TG_52_MAC1_RES_1_E,
    PRV_CPSS_TG_52_MAC1_RES_2_E,
    PRV_CPSS_TG_52_MAC1_RES_3_E,
    PRV_CPSS_TG_52_MAC1_RES_4_E,
    PRV_CPSS_TG_52_MAC1_RES_5_E,
    PRV_CPSS_TG_52_MAC1_RES_6_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT0_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT1_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT2_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT3_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT4_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT5_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT6_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT7_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT8_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT9_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT10_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT11_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT0_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT1_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT2_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT3_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT4_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT5_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT6_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT7_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT8_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT9_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT10_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT11_E,
    PRV_CPSS_TG_52_MAC1_RES_31_E,

    /* GOP 6                                */
    /* Indexes 672 - 703                    */
    PRV_CPSS_TG_52_GOP6_RES_0_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT12_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT13_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT14_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT15_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT16_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT17_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT18_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT19_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT20_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT21_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT22_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT23_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT24_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT25_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT26_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT12_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT13_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT14_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT15_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT16_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT17_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT18_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT19_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT20_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT21_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT22_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT23_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT24_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT25_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT26_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT52_E,

    /* GOP 7                                */
    /* Indexes 704 - 735                    */
    PRV_CPSS_TG_52_GOP7_RES_0_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT27_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT28_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT29_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT30_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT31_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT32_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT33_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT34_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT35_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT36_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT37_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT38_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT39_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT40_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT41_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT27_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT28_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT29_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT30_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT31_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT32_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT33_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT34_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT35_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT36_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT37_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT38_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT39_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT40_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT41_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT53_E,

    /* GOP 8                                */
    /* Indexes 736 - 767                    */
    PRV_CPSS_TG_52_GOP8_RES_0_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT42_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT43_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT44_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT45_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT46_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT47_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT48_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT49_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT50_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT51_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT52_E,
    PRV_CPSS_TG_52_TX_FIFO_UNDERRUN_PORT53_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT42_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT43_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT44_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT45_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT46_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT47_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT48_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT49_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT50_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT51_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT52_E,
    PRV_CPSS_TG_52_RX_FIFO_OVERRUN_PORT53_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT0_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT1_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT2_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT3_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT4_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT5_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT6_E,

    /* GOP 9                                */
    /* Indexes 768 - 799                    */
    PRV_CPSS_TG_52_GOP9_RES_0_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT7_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT8_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT9_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT10_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT11_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT12_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT13_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT14_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT15_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT16_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT17_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT18_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT19_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT20_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT21_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT22_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT23_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT24_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT25_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT26_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT27_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT28_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT29_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT30_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT31_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT32_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT33_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT34_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT35_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT36_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT37_E,

    /* GOP 10                               */
    /* Indexes 800 - 831                    */
    PRV_CPSS_TG_52_GOP10_RES_0_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT38_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT39_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT40_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT41_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT42_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT43_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT44_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT45_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT46_E,
    PRV_CPSS_TG_52_IPG_TOO_SMALL_PORT47_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT0_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT1_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT2_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT3_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT4_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT5_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT6_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT7_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT8_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT9_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT10_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT11_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT12_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT13_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT14_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT15_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT16_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT17_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT18_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT19_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT20_E,

    /* GOP 11                               */
    /* Indexes 832 - 863                    */
    PRV_CPSS_TG_52_GOP11_RES_0_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT21_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT22_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT23_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT24_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT25_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT26_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT27_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT28_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT29_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT30_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT31_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT32_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT33_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT34_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT35_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT36_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT37_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT38_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT39_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT40_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT41_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT42_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT43_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT44_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT45_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT46_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT47_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT48_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT49_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT50_E,
    PRV_CPSS_TG_52_ILLEGAL_SEQUENCE_PORT51_E,

    /* Indexes 864 - 895           */
    /* TXQ ExRMON Shadow Register Empty Interrupt Low ports 0-30 */
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_SUM_LOW_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT0_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT1_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT2_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT3_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT4_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT5_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT6_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT7_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT8_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT9_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT10_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT11_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT12_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT13_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT14_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT15_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT16_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT17_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT18_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT19_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT20_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT21_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT22_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT23_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT24_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT25_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT26_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT27_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT28_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT29_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT30_E,

    /* Indexes 896 - 927           */
    /* TXQ_EXRMON Shadow Register Empty Interrupt Low ports 31-51 */
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_SUM_HIGH_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT31_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT32_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT33_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT34_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT35_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT36_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT37_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT38_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT39_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT40_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT41_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT42_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT43_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT44_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT45_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT46_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT47_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT48_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT49_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT50_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT51_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_RES0_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_RES1_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_RES2_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_RES3_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_RES4_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_RES5_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_RES6_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_RES7_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_RES8_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_SHADOW_REG_EMPTY_RES9_E,


    /* Indexes 928 - 959           */
    /* TXQ_EXRMON Total Sample regs full Interrupt Low ports 0-30 */
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_SUM_LOW_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT0_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT1_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT2_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT3_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT4_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT5_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT6_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT7_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT8_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT9_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT10_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT11_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT12_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT13_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT14_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT15_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT16_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT17_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT18_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT19_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT20_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT21_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT22_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT23_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT24_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT25_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT26_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT27_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT28_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT29_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT30_E,

    /* Indexes 960 - 991           */
    /* TXQ EXRMON Total Sample regs full Interrupt Low ports 31-51 */
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_SUM_HIGH_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT31_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT32_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT33_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT34_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT35_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT36_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT37_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT38_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT39_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT40_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT41_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT42_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT43_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT44_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT45_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT46_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT47_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT48_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT49_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT50_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT51_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_RES0_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_RES1_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_RES2_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_RES3_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_RES4_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_RES5_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_RES6_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_RES7_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_RES8_E,
    PRV_CPSS_TG_52_TXQ_EXRMON_TOTAL_SAMP_FULL_RES9_E,

    /* Indexes 992 - 1023           */
    /* EPF ExRMON Shadow Register Empty Interrupt Low ports 0-30 */
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_SUM_LOW_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT0_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT1_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT2_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT3_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT4_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT5_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT6_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT7_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT8_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT9_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT10_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT11_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT12_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT13_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT14_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT15_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT16_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT17_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT18_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT19_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT20_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT21_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT22_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT23_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT24_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT25_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT26_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT27_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT28_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT29_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT30_E,

    /* Indexes 1024 - 1055           */
    /* EPF ExRMON Shadow Register Empty Interrupt Low ports 31-51 */
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_SUM_HIGH_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT31_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT32_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT33_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT34_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT35_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT36_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT37_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT38_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT39_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT40_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT41_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT42_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT43_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT44_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT45_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT46_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT47_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT48_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT49_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT50_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_PORT51_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_RES0_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_RES1_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_RES2_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_RES3_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_RES4_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_RES5_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_RES6_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_RES7_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_RES8_E,
    PRV_CPSS_TG_52_EPF_EXRMON_SHADOW_REG_EMPTY_RES9_E,


    /* Indexes 1056 - 1087           */
    /* EPF ExRMON Total Samp full Interrupt Low ports 0-30 */
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_SUM_LOW_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT0_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT1_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT2_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT3_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT4_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT5_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT6_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT7_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT8_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT9_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT10_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT11_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT12_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT13_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT14_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT15_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT16_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT17_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT18_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT19_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT20_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT21_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT22_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT23_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT24_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT25_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT26_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT27_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT28_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT29_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT30_E,

    /* Indexes 1088 - 1119           */
    /* EPF EXRMON Total Samp full Interrupt Low ports 31-51 */
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_SUM_HIGH_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT31_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT32_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT33_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT34_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT35_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT36_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT37_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT38_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT39_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT40_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT41_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT42_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT43_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT44_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT45_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT46_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT47_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT48_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT49_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT50_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_PORT51_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_RES0_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_RES1_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_RES2_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_RES3_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_RES4_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_RES5_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_RES6_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_RES7_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_RES8_E,
    PRV_CPSS_TG_52_EPF_EXRMON_TOTAL_SAMP_FULL_RES9_E,

    PRV_CPSS_TG_52_LAST_INT         /* should be always last in enum */

}PRV_CPSS_TG_52_INT_CAUSE_ENT;

/*
 * Typedef: enum GT_TD_XG_INT_CAUSE
 *
 * Description: All interrupt cause indexes_E, to be used for interrupts
 *              handling_E, and parameters change.
 *
 * NOTE : If needed_E, new interrupt bits can replace the XXX_RES_i bits_E, in case
 *        that these bits fall into the same cause registers.
 *
 *       Applicable devices: Tiger
 *                           XG       - 98EX136 , 98EX136DI
 *
 * Comment:
 *      Please see the description of each of the following interrupt event
 *      cause registers in the packet processor datasheet.
 */
typedef enum
{
    /* Summary and PCI interrupts   */
    /* Indexes 0 - 31               */
    PRV_CPSS_TG_XG_SUM_RES_0_E                       = 0,
    PRV_CPSS_TG_XG_MAS_READ_ERR_E,
    PRV_CPSS_TG_XG_SLV_WRITE_ERR_E,
    PRV_CPSS_TG_XG_MAS_WRITE_ERR_E,
    PRV_CPSS_TG_XG_ADDR_ERR_E,
    PRV_CPSS_TG_XG_MAS_ABORT_E,
    PRV_CPSS_TG_XG_TARGET_ABORT_E,
    PRV_CPSS_TG_XG_SLV_READ_ERR_E,
    PRV_CPSS_TG_XG_RETRY_CNTR_E,
    PRV_CPSS_TG_XG_SUM_RES_9_E,
    PRV_CPSS_TG_XG_SUM_RES_10_E,
    PRV_CPSS_TG_XG_SUM_RES_11_E,
    PRV_CPSS_TG_XG_SUM_RES_12_E,
    PRV_CPSS_TG_XG_SUM_RES_13_E,
    PRV_CPSS_TG_XG_SUM_RES_14_E,
    PRV_CPSS_TG_XG_SUM_RES_15_E,
    PRV_CPSS_TG_XG_SUM_RES_16_E,
    PRV_CPSS_TG_XG_SUM_RES_17_E,
    PRV_CPSS_TG_XG_SUM_RES_18_E,
    PRV_CPSS_TG_XG_SUM_RES_19_E,
    PRV_CPSS_TG_XG_SUM_RES_20_E,
    PRV_CPSS_TG_XG_SUM_RES_21_E,
    PRV_CPSS_TG_XG_SUM_RES_22_E,
    PRV_CPSS_TG_XG_SUM_RES_23_E,
    PRV_CPSS_TG_XG_SUM_RES_24_E,
    PRV_CPSS_TG_XG_SUM_RES_25_E,
    PRV_CPSS_TG_XG_SUM_RES_26_E,
    PRV_CPSS_TG_XG_SUM_RES_27_E,
    PRV_CPSS_TG_XG_SUM_RES_28_E,
    PRV_CPSS_TG_XG_SUM_RES_29_E,
    PRV_CPSS_TG_XG_SUM_RES_30_E,
    PRV_CPSS_TG_XG_SUM_RES_31_E,

    /* Ethernet Bridge interrupts   */
    /* Indexes 32 - 63              */
    PRV_CPSS_TG_XG_ETH_RES_0_E,
    PRV_CPSS_TG_XG_EB_NA_FIFO_FULL_E,
    PRV_CPSS_TG_XG_MAC_NUM_OF_HOP_EXP_E,
    PRV_CPSS_TG_XG_MAC_AGE_VIA_TRIGGER_ENDED_E,
    PRV_CPSS_TG_XG_MAC_NA_LEARNED_E,
    PRV_CPSS_TG_XG_MAC_NA_NOT_LEARNED_E,
    PRV_CPSS_TG_XG_MAC_TBL_READ_ECC_ERR_E,
    PRV_CPSS_TG_XG_EB_MG_ADDR_OUT_OF_RANGE_E,
    PRV_CPSS_TG_XG_EB_INGRESS_FILTER_PCKT_E,
    PRV_CPSS_TG_XG_EB_NA_NOT_LEARNED_SECURITY_BREACH_E,
    PRV_CPSS_TG_XG_ETH_RES_10_E,
    PRV_CPSS_TG_XG_ETH_RES_11_E,
    PRV_CPSS_TG_XG_ETH_RES_12_E,
    PRV_CPSS_TG_XG_ETH_RES_13_E,
    PRV_CPSS_TG_XG_ETH_RES_14_E,
    PRV_CPSS_TG_XG_ETH_RES_15_E,
    PRV_CPSS_TG_XG_ETH_RES_16_E,
    PRV_CPSS_TG_XG_ETH_RES_17_E,
    PRV_CPSS_TG_XG_ETH_RES_18_E,
    PRV_CPSS_TG_XG_ETH_RES_19_E,
    PRV_CPSS_TG_XG_ETH_RES_20_E,
    PRV_CPSS_TG_XG_ETH_RES_21_E,
    PRV_CPSS_TG_XG_ETH_RES_22_E,
    PRV_CPSS_TG_XG_ETH_RES_23_E,
    PRV_CPSS_TG_XG_ETH_RES_24_E,
    PRV_CPSS_TG_XG_ETH_RES_25_E,
    PRV_CPSS_TG_XG_ETH_RES_26_E,
    PRV_CPSS_TG_XG_ETH_RES_27_E,
    PRV_CPSS_TG_XG_ETH_RES_28_E,
    PRV_CPSS_TG_XG_ETH_RES_29_E,
    PRV_CPSS_TG_XG_ETH_RES_30_E,
    PRV_CPSS_TG_XG_ETH_RES_31_E,


    /* Lx Unit related interrupts           */
    /* Indexes 64 - 95                      */
    PRV_CPSS_TG_XG_LX_RES_0_E,
    PRV_CPSS_TG_XG_LX_LB_ERR_E,
    PRV_CPSS_TG_XG_LX_RES_2_E,
    PRV_CPSS_TG_XG_LX_RES_3_E,
    PRV_CPSS_TG_XG_LX_RES_4_E,
    PRV_CPSS_TG_XG_LX_RES_5_E,
    PRV_CPSS_TG_XG_LX_RES_6_E,
    PRV_CPSS_TG_XG_LX_TC_2_RF_CNTR_ALRM_E,
    PRV_CPSS_TG_XG_LX_TC_2_RF_PLC_ALRM_E,
    PRV_CPSS_TG_XG_LX_TC_2_RF_TBL_ERR_E,
    PRV_CPSS_TG_XG_LX_CTRL_MEM_2_RF_ERR_E,
    PRV_CPSS_TG_XG_LX_TCB_CNTR_E,
    PRV_CPSS_TG_XG_LX_RES_12_E,
    PRV_CPSS_TG_XG_LX_RES_13_E,
    PRV_CPSS_TG_XG_LX_RES_14_E,
    PRV_CPSS_TG_XG_LX_RES_15_E,
    PRV_CPSS_TG_XG_LX_IPV4_REFRESH_AGE_OVERRUN_E,
    PRV_CPSS_TG_XG_LX_IPV4_LPM_ERR_0_E,
    PRV_CPSS_TG_XG_LX_IPV4_LPM_ERR_1_E,
    PRV_CPSS_TG_XG_LX_IPV4_LPM_ERR_2_E,
    PRV_CPSS_TG_XG_LX_IPV4_LPM_ERR_3_E,
    PRV_CPSS_TG_XG_LX_IPV4_LPM_ERR_4_E,
    PRV_CPSS_TG_XG_LX_IPV4_ROUTE_ERR_E,
    PRV_CPSS_TG_XG_LX_IPV4_CNTR_E,
    PRV_CPSS_TG_XG_LX_IPV4_CNTR_SECOND_E,
    PRV_CPSS_TG_XG_LX_RES_25_E,
    PRV_CPSS_TG_XG_LX_RES_26_E,
    PRV_CPSS_TG_XG_LX_PCE_PAR_ERR_E,
    PRV_CPSS_TG_XG_LX_TCAM_MISS1_E,
    PRV_CPSS_TG_XG_LX_TCAM_MISS2_E,
    PRV_CPSS_TG_XG_LX_TCAM_MISS3_E,
    PRV_CPSS_TG_XG_LX_L3_L7_ERR_ADDR_E,


    /* Buffer Management related interrupts */
    /* Indexes 96 - 127                     */
    PRV_CPSS_TG_XG_BM_RES_0_E,
    PRV_CPSS_TG_XG_BM_MAX_BUFF_REACHED_PORT0_E,
    PRV_CPSS_TG_XG_BM_RES_2_E,
    PRV_CPSS_TG_XG_BM_RES_3_E,
    PRV_CPSS_TG_XG_BM_RES_4_E,
    PRV_CPSS_TG_XG_BM_RES_5_E,
    PRV_CPSS_TG_XG_BM_RES_6_E,
    PRV_CPSS_TG_XG_BM_RES_7_E,
    PRV_CPSS_TG_XG_BM_RES_8_E,
    PRV_CPSS_TG_XG_BM_RES_9_E,
    PRV_CPSS_TG_XG_BM_RES_10_E,
    PRV_CPSS_TG_XG_BM_RES_11_E,
    PRV_CPSS_TG_XG_BM_RES_12_E,
    PRV_CPSS_TG_XG_LOCAL_RECLAIM_E,
    PRV_CPSS_TG_XG_LOCAL_RXBUFF_FULL_E,
    PRV_CPSS_TG_XG_LINE_IND_ERR_E,
    PRV_CPSS_TG_XG_CLEAR_CNT_ERR_E,
    PRV_CPSS_TG_XG_CLEAR_BIT_MAP_ERR_E,
    PRV_CPSS_TG_XG_LONG_ALLOC_CL_BIT_ERR_E,
    PRV_CPSS_TG_XG_SHORT_ALLOC_CL_BIT_ERR_E,
    PRV_CPSS_TG_XG_MULTI_CNT_INC_ERR_E,
    PRV_CPSS_TG_XG_MULTI_CNT_DEC_ERR_E,
    PRV_CPSS_TG_XG_BM_INVALID_ADDRESS_E,
    PRV_CPSS_TG_XG_RX_MEM_WRITE_OVERRUN_E,
    PRV_CPSS_TG_XG_RX_MEM_READ_UNDERRUN_E,
    PRV_CPSS_TG_XG_BM_RX_MEM_READ_ECC_ERROR_E,
    PRV_CPSS_TG_XG_RX_DESC_NO_HEADER_E,
    PRV_CPSS_TG_XG_BM_VLT_ECC_ERR_E,
    PRV_CPSS_TG_XG_CPU_BUFF_FULL_E,
    PRV_CPSS_TG_XG_BM_UPLINK_GPP_E,
    PRV_CPSS_TG_XG_BM_RES_30_E,
    PRV_CPSS_TG_XG_BM_RES_31_E,

    /* Buffer Management related interrupts */
    /* Cause 2                              */
    /* Indexes 128 - 159                    */
    PRV_CPSS_TG_XG_BM2_RES_0_E,
    PRV_CPSS_TG_XG_BM2_RES_1_E,
    PRV_CPSS_TG_XG_BM2_RES_2_E,
    PRV_CPSS_TG_XG_BM2_RES_3_E,
    PRV_CPSS_TG_XG_BM2_RES_4_E,
    PRV_CPSS_TG_XG_BM2_RES_5_E,
    PRV_CPSS_TG_XG_BM2_RES_6_E,
    PRV_CPSS_TG_XG_BM2_RES_7_E,
    PRV_CPSS_TG_XG_BM2_RES_8_E,
    PRV_CPSS_TG_XG_BM2_RES_9_E,
    PRV_CPSS_TG_XG_BM_VLT_ECC_ERR_FIXED_INT_E,
    PRV_CPSS_TG_XG_BM2_RES_11_E,
    PRV_CPSS_TG_XG_BM2_RES_12_E,
    PRV_CPSS_TG_XG_BM2_RES_13_E,
    PRV_CPSS_TG_XG_BM2_RES_14_E,
    PRV_CPSS_TG_XG_BM2_RES_15_E,
    PRV_CPSS_TG_XG_BM2_RES_16_E,
    PRV_CPSS_TG_XG_BM2_RES_17_E,
    PRV_CPSS_TG_XG_BM2_RES_18_E,
    PRV_CPSS_TG_XG_BM2_RES_19_E,
    PRV_CPSS_TG_XG_BM2_RES_20_E,
    PRV_CPSS_TG_XG_BM2_RES_21_E,
    PRV_CPSS_TG_XG_BM2_RES_22_E,
    PRV_CPSS_TG_XG_BM2_RES_23_E,
    PRV_CPSS_TG_XG_BM2_RES_24_E,
    PRV_CPSS_TG_XG_BM2_RES_25_E,
    PRV_CPSS_TG_XG_BM2_RES_26_E,
    PRV_CPSS_TG_XG_BM2_RES_27_E,
    PRV_CPSS_TG_XG_BM2_RES_28_E,
    PRV_CPSS_TG_XG_BM2_RES_29_E,
    PRV_CPSS_TG_XG_BM2_RES_30_E,
    PRV_CPSS_TG_XG_BM2_RES_31_E,

    /* MAC related interrupts               */
    /* Indexes 160 - 191                    */
    PRV_CPSS_TG_XG_MAC0_RES_0_E,
    PRV_CPSS_TG_XG_RX_FIFO_OVERRUN_PORT0_E,
    PRV_CPSS_TG_XG_TX_FIFO_UNDERRUN_PORT0_E,
    PRV_CPSS_TG_XG_RX_FIFO_OVERRUN_PORT5_E,
    PRV_CPSS_TG_XG_TX_FIFO_UNDERRUN_PORT5_E,
    PRV_CPSS_TG_XG_MAC0_RES_5_E,
    PRV_CPSS_TG_XG_MAC0_RES_6_E,
    PRV_CPSS_TG_XG_MAC0_RES_7_E,
    PRV_CPSS_TG_XG_MAC0_RES_8_E,
    PRV_CPSS_TG_XG_MAC0_RES_9_E,
    PRV_CPSS_TG_XG_MAC0_RES_10_E,
    PRV_CPSS_TG_XG_MAC0_RES_11_E,
    PRV_CPSS_TG_XG_MAC0_RES_12_E,
    PRV_CPSS_TG_XG_MAC0_RES_13_E,
    PRV_CPSS_TG_XG_MAC0_RES_14_E,
    PRV_CPSS_TG_XG_MAC0_RES_15_E,
    PRV_CPSS_TG_XG_MAC0_RES_16_E,
    PRV_CPSS_TG_XG_MAC0_RES_17_E,
    PRV_CPSS_TG_XG_MAC0_RES_18_E,
    PRV_CPSS_TG_XG_MAC0_RES_19_E,
    PRV_CPSS_TG_XG_FC_STAT_CHANGE_E,
    PRV_CPSS_TG_XG_MAC_SFLOW_E,
    PRV_CPSS_TG_XG_PORT_CONSECUTIVE_TERM_CODE_E,
    PRV_CPSS_TG_XG_ILLEGAL_SEQUENCE_PORT0_E,
    PRV_CPSS_TG_XG_PORT_FAULT_TYPE_CHANGE_E,
    PRV_CPSS_TG_XG_MDIO_NOT_BUSY_E,
    PRV_CPSS_TG_XG_MAC0_RES_26_E,
    PRV_CPSS_TG_XG_GPP_INTERRUPT1_E,
    PRV_CPSS_TG_XG_GPP_INTERRUPT2_E,
    PRV_CPSS_TG_XG_GPP_INTERRUPT3_E,
    PRV_CPSS_TG_XG_MAC_MG_ADDR_OUT_OF_RANGE_E,
    PRV_CPSS_TG_XG_COUNT_EXPIRED_E,


    /* Transmit Queues related interrupts   */
    /* Cause 0                              */
    /* Indexes 192 - 223                   */
    PRV_CPSS_TG_XG_TXQ_RES_0_E,
    PRV_CPSS_TG_XG_TQ_WATCHDOG_EX_PORT0_E,
    PRV_CPSS_TG_XG_TXQ_RES_2_E,
    PRV_CPSS_TG_XG_TXQ_RES_3_E,
    PRV_CPSS_TG_XG_TXQ_RES_4_E,
    PRV_CPSS_TG_XG_TXQ_RES_5_E,
    PRV_CPSS_TG_XG_TXQ_RES_6_E,
    PRV_CPSS_TG_XG_TXQ_RES_7_E,
    PRV_CPSS_TG_XG_TXQ_RES_8_E,
    PRV_CPSS_TG_XG_TXQ_RES_9_E,
    PRV_CPSS_TG_XG_TXQ_RES_10_E,
    PRV_CPSS_TG_XG_TQ_TXQ2_FLUSH_PORT0_E,
    PRV_CPSS_TG_XG_TXQ_RES_12_E,
    PRV_CPSS_TG_XG_TXQ_RES_13_E,
    PRV_CPSS_TG_XG_TXQ_RES_14_E,
    PRV_CPSS_TG_XG_TXQ_RES_15_E,
    PRV_CPSS_TG_XG_TXQ_RES_16_E,
    PRV_CPSS_TG_XG_TXQ_RES_17_E,
    PRV_CPSS_TG_XG_TXQ_RES_18_E,
    PRV_CPSS_TG_XG_TXQ_RES_19_E,
    PRV_CPSS_TG_XG_TXQ_RES_20_E,
    PRV_CPSS_TG_XG_TQ_TXQ2_MG_FLUSH_E,
    PRV_CPSS_TG_XG_TQ_LINK_LIST_ECC_ERR_HI_E,
    PRV_CPSS_TG_XG_TQ_LINK_LIST_ECC_ERR_LO_E,
    PRV_CPSS_TG_XG_TQ_MLL_PARITY_ERR_E,
    PRV_CPSS_TG_XG_TQ_MG_READ_ERR_E,
    PRV_CPSS_TG_XG_TXQ_RES_26_E,
    PRV_CPSS_TG_XG_TXQ_RES_27_E,
    PRV_CPSS_TG_XG_TXQ_RES_28_E,
    PRV_CPSS_TG_XG_TXQ_RES_29_E,
    PRV_CPSS_TG_XG_TXQ_RES_30_E,
    PRV_CPSS_TG_XG_TXQ_RES_31_E,

    /* Cause 1                             */
    /* Indexes 224 - 255                   */
    PRV_CPSS_TG_XG_TXQ1_RES_0_E,
    PRV_CPSS_TG_XG_TXQ1_RES_1_E,
    PRV_CPSS_TG_XG_TXQ1_RES_2_E,
    PRV_CPSS_TG_XG_TXQ1_RES_3_E,
    PRV_CPSS_TG_XG_TXQ1_RES_4_E,
    PRV_CPSS_TG_XG_TXQ1_RES_5_E,
    PRV_CPSS_TG_XG_TXQ1_RES_6_E,
    PRV_CPSS_TG_XG_TXQ1_RES_7_E,
    PRV_CPSS_TG_XG_TXQ1_RES_8_E,
    PRV_CPSS_TG_XG_TXQ1_RES_9_E,
    PRV_CPSS_TG_XG_TXQ1_RES_10_E,
    PRV_CPSS_TG_XG_TXQ1_RES_11_E,
    PRV_CPSS_TG_XG_TXQ1_RES_12_E,
    PRV_CPSS_TG_XG_TXQ1_RES_13_E,
    PRV_CPSS_TG_XG_TXQ1_RES_14_E,
    PRV_CPSS_TG_XG_TXQ1_RES_15_E,
    PRV_CPSS_TG_XG_TXQ1_RES_16_E,
    PRV_CPSS_TG_XG_TXQ1_RES_17_E,
    PRV_CPSS_TG_XG_TXQ1_RES_18_E,
    PRV_CPSS_TG_XG_TXQ1_RES_19_E,
    PRV_CPSS_TG_XG_TXQ1_RES_20_E,
    PRV_CPSS_TG_XG_TXQ1_RES_21_E,
    PRV_CPSS_TG_XG_TXQ1_RES_22_E,
    PRV_CPSS_TG_XG_TXQ1_RES_23_E,
    PRV_CPSS_TG_XG_TXQ1_RES_24_E,
    PRV_CPSS_TG_XG_TXQ1_RES_25_E,
    PRV_CPSS_TG_XG_TXQ1_RES_26_E,
    PRV_CPSS_TG_XG_TXQ1_RES_27_E,
    PRV_CPSS_TG_XG_TXQ1_RES_28_E,
    PRV_CPSS_TG_XG_TXQ1_RES_29_E,
    PRV_CPSS_TG_XG_TXQ1_RES_30_E,
    PRV_CPSS_TG_XG_TXQ1_RES_31_E,

    /* Cause 3                             */
    /* Indexes 256 - 287                   */
    PRV_CPSS_TG_XG_TXQ3_RES_0_E,
    PRV_CPSS_TG_XG_TXQ3_RES_1_E,
    PRV_CPSS_TG_XG_TXQ3_RES_2_E,
    PRV_CPSS_TG_XG_TXQ3_RES_3_E,
    PRV_CPSS_TG_XG_TXQ3_RES_4_E,
    PRV_CPSS_TG_XG_TXQ3_RES_5_E,
    PRV_CPSS_TG_XG_TXQ3_RES_6_E,
    PRV_CPSS_TG_XG_TXQ3_RES_7_E,
    PRV_CPSS_TG_XG_TXQ3_RES_8_E,
    PRV_CPSS_TG_XG_TXQ3_RES_9_E,
    PRV_CPSS_TG_XG_TXQ3_RES_10_E,
    PRV_CPSS_TG_XG_TXQ3_RES_11_E,
    PRV_CPSS_TG_XG_TXQ3_RES_12_E,
    PRV_CPSS_TG_XG_TXQ3_RES_13_E,
    PRV_CPSS_TG_XG_TXQ3_RES_14_E,
    PRV_CPSS_TG_XG_TXQ3_RES_15_E,
    PRV_CPSS_TG_XG_TXQ3_RES_16_E,
    PRV_CPSS_TG_XG_TXQ3_RES_17_E,
    PRV_CPSS_TG_XG_TXQ3_RES_18_E,
    PRV_CPSS_TG_XG_TXQ3_RES_19_E,
    PRV_CPSS_TG_XG_TXQ3_RES_20_E,
    PRV_CPSS_TG_XG_TXQ3_RES_21_E,
    PRV_CPSS_TG_XG_TXQ3_RES_22_E,
    PRV_CPSS_TG_XG_TXQ3_RES_23_E,
    PRV_CPSS_TG_XG_TXQ3_RES_24_E,
    PRV_CPSS_TG_XG_TXQ3_RES_25_E,
    PRV_CPSS_TG_XG_TXQ3_RES_26_E,
    PRV_CPSS_TG_XG_TQ_MC_FIFO_OVERRUN_E,
    PRV_CPSS_TG_XG_TQ_TOTAL_DESC_UNDERFLOW_E,
    PRV_CPSS_TG_XG_TQ_TOTAL_DESC_OVERFLOW_E,
    PRV_CPSS_TG_XG_TQ_SNIFF_DESC_DROP_E,
    PRV_CPSS_TG_XG_MC_FIFO_FULL_E,


    /* Cause 4                             */
    /* Indexes 288 - 319                    */
    PRV_CPSS_TG_XG_TXQ4_RES_0_E,
    PRV_CPSS_TG_XG_PORT0_TQ_RED_REACHED_E,
    PRV_CPSS_TG_XG_TXQ4_RES_2_E,
    PRV_CPSS_TG_XG_TXQ4_RES_3_E,
    PRV_CPSS_TG_XG_TXQ4_RES_4_E,
    PRV_CPSS_TG_XG_TXQ4_RES_5_E,
    PRV_CPSS_TG_XG_TXQ4_RES_6_E,
    PRV_CPSS_TG_XG_TXQ4_RES_7_E,
    PRV_CPSS_TG_XG_TXQ4_RES_8_E,
    PRV_CPSS_TG_XG_TXQ4_RES_9_E,
    PRV_CPSS_TG_XG_TXQ4_RES_10_E,
    PRV_CPSS_TG_XG_TXQ4_RES_11_E,
    PRV_CPSS_TG_XG_TXQ4_RES_12_E,
    PRV_CPSS_TG_XG_TXQ4_RES_13_E,
    PRV_CPSS_TG_XG_TXQ4_RES_14_E,
    PRV_CPSS_TG_XG_TXQ4_RES_15_E,
    PRV_CPSS_TG_XG_TXQ4_RES_16_E,
    PRV_CPSS_TG_XG_TXQ4_RES_17_E,
    PRV_CPSS_TG_XG_TXQ4_RES_18_E,
    PRV_CPSS_TG_XG_TXQ4_RES_19_E,
    PRV_CPSS_TG_XG_TXQ4_RES_20_E,
    PRV_CPSS_TG_XG_TXQ4_RES_21_E,
    PRV_CPSS_TG_XG_TXQ4_RES_22_E,
    PRV_CPSS_TG_XG_TXQ4_RES_23_E,
    PRV_CPSS_TG_XG_TXQ4_RES_24_E,
    PRV_CPSS_TG_XG_TXQ4_RES_25_E,
    PRV_CPSS_TG_XG_TXQ4_RES_26_E,
    PRV_CPSS_TG_XG_TXQ4_RES_27_E,
    PRV_CPSS_TG_XG_TXQ4_RES_28_E,
    PRV_CPSS_TG_XG_TXQ4_RES_29_E,
    PRV_CPSS_TG_XG_TXQ4_RES_30_E,
    PRV_CPSS_TG_XG_TXQ4_RES_31_E,

    /* Cause 5                             */
    /* Indexes 320 - 351                    */
    PRV_CPSS_TG_XG_TXQ5_RES_0_E,
    PRV_CPSS_TG_XG_TXQ5_RES_1_E,
    PRV_CPSS_TG_XG_TXQ5_RES_2_E,
    PRV_CPSS_TG_XG_TXQ5_RES_3_E,
    PRV_CPSS_TG_XG_TXQ5_RES_4_E,
    PRV_CPSS_TG_XG_TXQ5_RES_5_E,
    PRV_CPSS_TG_XG_TXQ5_RES_6_E,
    PRV_CPSS_TG_XG_TXQ5_RES_7_E,
    PRV_CPSS_TG_XG_TXQ5_RES_8_E,
    PRV_CPSS_TG_XG_TXQ5_RES_9_E,
    PRV_CPSS_TG_XG_TXQ5_RES_10_E,
    PRV_CPSS_TG_XG_TXQ5_RES_11_E,
    PRV_CPSS_TG_XG_TXQ5_RES_12_E,
    PRV_CPSS_TG_XG_TXQ5_RES_13_E,
    PRV_CPSS_TG_XG_TXQ5_RES_14_E,
    PRV_CPSS_TG_XG_TXQ5_RES_15_E,
    PRV_CPSS_TG_XG_TXQ5_RES_16_E,
    PRV_CPSS_TG_XG_TXQ5_RES_17_E,
    PRV_CPSS_TG_XG_TXQ5_RES_18_E,
    PRV_CPSS_TG_XG_TXQ5_RES_19_E,
    PRV_CPSS_TG_XG_TXQ5_RES_20_E,
    PRV_CPSS_TG_XG_TXQ5_RES_21_E,
    PRV_CPSS_TG_XG_TXQ5_RES_22_E,
    PRV_CPSS_TG_XG_TQ_RED_REACHED_PORT_CPU_63_E,
    PRV_CPSS_TG_XG_TXQ5_RES_24_E,
    PRV_CPSS_TG_XG_TXQ5_RES_25_E,
    PRV_CPSS_TG_XG_TXQ5_RES_26_E,
    PRV_CPSS_TG_XG_TXQ5_RES_27_E,
    PRV_CPSS_TG_XG_TXQ5_RES_28_E,
    PRV_CPSS_TG_XG_TXQ5_RES_29_E,
    PRV_CPSS_TG_XG_TXQ5_RES_30_E,
    PRV_CPSS_TG_XG_TXQ5_RES_31_E,

    /* Miscellaneous interrupts             */
    /* Indexes 352 - 383                    */
    PRV_CPSS_TG_XG_MISC_RES_0_E,
    PRV_CPSS_TG_XG_MAC_AUQ_PENDING_E,
    PRV_CPSS_TG_XG_EB_AUQ_FULL_E,
    PRV_CPSS_TG_XG_DRQ_PENDING_E,
    PRV_CPSS_TG_XG_MISC_RES_4_E,
    PRV_CPSS_TG_XG_MAC_AU_PROCESSED_E,
    PRV_CPSS_TG_XG_MISC_C2C_W_FAR_END_UP_E,
    PRV_CPSS_TG_XG_MISC_C2C_N_FAR_END_UP_E,
    PRV_CPSS_TG_XG_MISC_C2C_DATA_ERR_E,
    PRV_CPSS_TG_XG_MISC_MSG_TIME_OUT_E,
    PRV_CPSS_TG_XG_MISC_ILLEGAL_ADDR_E,
    PRV_CPSS_TG_XG_MISC_RES_11_E,
    PRV_CPSS_TG_XG_MISC_RES_12_E,
    PRV_CPSS_TG_XG_MISC_RES_13_E,
    PRV_CPSS_TG_XG_MISC_RES_14_E,
    PRV_CPSS_TG_XG_MISC_RES_15_E,
    PRV_CPSS_TG_XG_DRQ_EMPTY_E,
    PRV_CPSS_TG_XG_AUQ_OVERRUN_E,
    PRV_CPSS_TG_XG_UPLINK_W_ECC_ON_DATA_E,
    PRV_CPSS_TG_XG_UPLINK_W_ECC_ON_HEADER_E,
    PRV_CPSS_TG_XG_UPLINK_W_RX_FIFO_OVERRUN_E,
    PRV_CPSS_TG_XG_UPLINK_N_ECC_ON_DATA_E,
    PRV_CPSS_TG_XG_UPLINK_N_ECC_ON_HEADER_E,
    PRV_CPSS_TG_XG_UPLINK_N_RX_FIFO_OVERRUN_E,
    PRV_CPSS_TG_XG_AUQ_ALMOST_FULL_E,
    PRV_CPSS_TG_XG_MISC_RES_25_E,
    PRV_CPSS_TG_XG_MISC_RES_26_E,
    PRV_CPSS_TG_XG_MISC_RES_27_E,
    PRV_CPSS_TG_XG_MISC_RES_28_E,
    PRV_CPSS_TG_XG_MISC_RES_29_E,
    PRV_CPSS_TG_XG_MISC_RES_30_E,
    PRV_CPSS_TG_XG_MISC_RES_31_E,


    /* Rx SDMA related interrupts           */
    /* Indexes 384 - 415                     */
    PRV_CPSS_TG_XG_RX_RES_0_E,
    PRV_CPSS_TG_XG_RX_RES_1_E,
    PRV_CPSS_TG_XG_RX_BUFFER_QUEUE0_E,
    PRV_CPSS_TG_XG_RX_BUFFER_QUEUE1_E,
    PRV_CPSS_TG_XG_RX_BUFFER_QUEUE2_E,
    PRV_CPSS_TG_XG_RX_BUFFER_QUEUE3_E,
    PRV_CPSS_TG_XG_RX_BUFFER_QUEUE4_E,
    PRV_CPSS_TG_XG_RX_BUFFER_QUEUE5_E,
    PRV_CPSS_TG_XG_RX_BUFFER_QUEUE6_E,
    PRV_CPSS_TG_XG_RX_BUFFER_QUEUE7_E,
    PRV_CPSS_TG_XG_RX_RES_10_E,
    PRV_CPSS_TG_XG_RX_ERR_QUEUE0_E,
    PRV_CPSS_TG_XG_RX_ERR_QUEUE1_E,
    PRV_CPSS_TG_XG_RX_ERR_QUEUE2_E,
    PRV_CPSS_TG_XG_RX_ERR_QUEUE3_E,
    PRV_CPSS_TG_XG_RX_ERR_QUEUE4_E,
    PRV_CPSS_TG_XG_RX_ERR_QUEUE5_E,
    PRV_CPSS_TG_XG_RX_ERR_QUEUE6_E,
    PRV_CPSS_TG_XG_RX_ERR_QUEUE7_E,
    PRV_CPSS_TG_XG_RESOURCES_ERR_CNT_OF_E,
    PRV_CPSS_TG_XG_BYTE_CNT_OF_E,
    PRV_CPSS_TG_XG_PACKET_CNT_OF_E,
    PRV_CPSS_TG_XG_RX_RES_22_E,
    PRV_CPSS_TG_XG_RX_RES_23_E,
    PRV_CPSS_TG_XG_RX_RES_24_E,
    PRV_CPSS_TG_XG_RX_RES_25_E,
    PRV_CPSS_TG_XG_RX_RES_26_E,
    PRV_CPSS_TG_XG_RX_RES_27_E,
    PRV_CPSS_TG_XG_RX_RES_28_E,
    PRV_CPSS_TG_XG_RX_RES_29_E,
    PRV_CPSS_TG_XG_RX_RES_30_E,
    PRV_CPSS_TG_XG_RX_RES_31_E,


    /* Tx SDMA related interrupts           */
    /* Indexes 416 - 447           */
    PRV_CPSS_TG_XG_TX_RES_0_E,
    PRV_CPSS_TG_XG_TX_BUFFER_QUEUE0_E,
    PRV_CPSS_TG_XG_TX_BUFFER_QUEUE1_E,
    PRV_CPSS_TG_XG_TX_BUFFER_QUEUE2_E,
    PRV_CPSS_TG_XG_TX_BUFFER_QUEUE3_E,
    PRV_CPSS_TG_XG_TX_BUFFER_QUEUE4_E,
    PRV_CPSS_TG_XG_TX_BUFFER_QUEUE5_E,
    PRV_CPSS_TG_XG_TX_BUFFER_QUEUE6_E,
    PRV_CPSS_TG_XG_TX_BUFFER_QUEUE7_E,
    PRV_CPSS_TG_XG_TX_ERR_QUEUE0_E,
    PRV_CPSS_TG_XG_TX_ERR_QUEUE1_E,
    PRV_CPSS_TG_XG_TX_ERR_QUEUE2_E,
    PRV_CPSS_TG_XG_TX_ERR_QUEUE3_E,
    PRV_CPSS_TG_XG_TX_ERR_QUEUE4_E,
    PRV_CPSS_TG_XG_TX_ERR_QUEUE5_E,
    PRV_CPSS_TG_XG_TX_ERR_QUEUE6_E,
    PRV_CPSS_TG_XG_TX_ERR_QUEUE7_E,
    PRV_CPSS_TG_XG_TX_END_QUEUE0_E,
    PRV_CPSS_TG_XG_TX_END_QUEUE1_E,
    PRV_CPSS_TG_XG_TX_END_QUEUE2_E,
    PRV_CPSS_TG_XG_TX_END_QUEUE3_E,
    PRV_CPSS_TG_XG_TX_END_QUEUE4_E,
    PRV_CPSS_TG_XG_TX_END_QUEUE5_E,
    PRV_CPSS_TG_XG_TX_END_QUEUE6_E,
    PRV_CPSS_TG_XG_TX_END_QUEUE7_E,
    PRV_CPSS_TG_XG_TX_RES_25_E,
    PRV_CPSS_TG_XG_TX_RES_26_E,
    PRV_CPSS_TG_XG_TX_RES_27_E,
    PRV_CPSS_TG_XG_TX_RES_28_E,
    PRV_CPSS_TG_XG_TX_RES_29_E,
    PRV_CPSS_TG_XG_TX_RES_30_E,
    PRV_CPSS_TG_XG_TX_RES_31_E,

    /* MAC1 related interrupts.              */
    /* Indexes 448 - 479           */
    PRV_CPSS_TG_XG_MAC1_RES_0_E,
    PRV_CPSS_TG_XG_MAC1_RES_1_E,
    PRV_CPSS_TG_XG_MAC1_RES_2_E,
    PRV_CPSS_TG_XG_MAC1_RES_3_E,
    PRV_CPSS_TG_XG_MAC1_RES_4_E,
    PRV_CPSS_TG_XG_MAC1_RES_5_E,
    PRV_CPSS_TG_XG_MAC1_RES_6_E,
    PRV_CPSS_TG_XG_MAC1_RES_7_E,
    PRV_CPSS_TG_XG_MAC1_RES_8_E,
    PRV_CPSS_TG_XG_MAC1_RES_9_E,
    PRV_CPSS_TG_XG_MAC1_RES_10_E,
    PRV_CPSS_TG_XG_MAC1_RES_11_E,
    PRV_CPSS_TG_XG_MAC1_RES_12_E,
    PRV_CPSS_TG_XG_MAC1_RES_13_E,
    PRV_CPSS_TG_XG_MAC1_RES_14_E,
    PRV_CPSS_TG_XG_MAC1_RES_15_E,
    PRV_CPSS_TG_XG_MAC1_RES_16_E,
    PRV_CPSS_TG_XG_MAC1_RES_17_E,
    PRV_CPSS_TG_XG_MAC1_RES_18_E,
    PRV_CPSS_TG_XG_MAC1_RES_19_E,
    PRV_CPSS_TG_XG_MAC1_RES_20_E,
    PRV_CPSS_TG_XG_MAC1_RES_21_E,
    PRV_CPSS_TG_XG_MAC1_RES_22_E,
    PRV_CPSS_TG_XG_MAC1_RES_23_E,
    PRV_CPSS_TG_XG_MAC1_RES_24_E,
    PRV_CPSS_TG_XG_MAC1_RES_25_E,
    PRV_CPSS_TG_XG_MAC1_RES_26_E,
    PRV_CPSS_TG_XG_MAC1_RES_27_E,
    PRV_CPSS_TG_XG_MAC1_RES_28_E,
    PRV_CPSS_TG_XG_MAC1_RES_29_E,
    PRV_CPSS_TG_XG_MAC1_RES_30_E,
    PRV_CPSS_TG_XG_MAC1_RES_31_E,

    /* Indexes 512 - 543           */
    /* TXQ ExRMON Shadow Register Empty Interrupt Low ports 0-30 */
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_SUM_LOW_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT0_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT1_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT2_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT3_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT4_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT5_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT6_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT7_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT8_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT9_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT10_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT11_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT12_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT13_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT14_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT15_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT16_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT17_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT18_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT19_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT20_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT21_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT22_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT23_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT24_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT25_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT26_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT27_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT28_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT29_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT30_E,

    /* Indexes 480 - 511           */
    /* TXQ_EXRMON Shadow Register Empty Interrupt Low ports 31-51 */
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_SUM_HIGH_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT31_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT32_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT33_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT34_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT35_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT36_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT37_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT38_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT39_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT40_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT41_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT42_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT43_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT44_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT45_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT46_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT47_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT48_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT49_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT50_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_PORT51_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_RES0_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_RES1_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_RES2_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_RES3_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_RES4_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_RES5_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_RES6_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_RES7_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_RES8_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_SHADOW_REG_EMPTY_RES9_E,


    /* Indexes 544 - 575           */
    /* TXQ_EXRMON Total Sample regs full Interrupt Low ports 0-30 */
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_SUM_LOW_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT0_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT1_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT2_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT3_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT4_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT5_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT6_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT7_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT8_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT9_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT10_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT11_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT12_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT13_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT14_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT15_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT16_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT17_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT18_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT19_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT20_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT21_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT22_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT23_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT24_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT25_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT26_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT27_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT28_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT29_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT30_E,

    /* Indexes 576 - 607           */
    /* TXQ EXRMON Total Sample regs full Interrupt Low ports 31-51 */
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_SUM_HIGH_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT31_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT32_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT33_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT34_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT35_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT36_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT37_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT38_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT39_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT40_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT41_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT42_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT43_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT44_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT45_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT46_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT47_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT48_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT49_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT50_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_PORT51_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_RES0_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_RES1_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_RES2_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_RES3_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_RES4_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_RES5_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_RES6_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_RES7_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_RES8_E,
    PRV_CPSS_TG_XG_TXQ_EXRMON_TOTAL_SAMP_FULL_RES9_E,

    /* Indexes 608 - 639           */
    /* EPF ExRMON Shadow Register Empty Interrupt Low ports 0-30 */
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_SUM_LOW_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT0_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT1_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT2_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT3_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT4_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT5_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT6_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT7_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT8_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT9_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT10_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT11_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT12_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT13_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT14_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT15_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT16_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT17_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT18_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT19_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT20_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT21_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT22_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT23_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT24_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT25_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT26_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT27_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT28_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT29_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT30_E,

    /* Indexes 640 - 671           */
    /* EPF ExRMON Shadow Register Empty Interrupt Low ports 31-51 */
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_SUM_HIGH_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT31_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT32_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT33_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT34_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT35_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT36_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT37_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT38_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT39_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT40_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT41_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT42_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT43_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT44_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT45_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT46_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT47_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT48_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT49_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT50_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_PORT51_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_RES0_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_RES1_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_RES2_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_RES3_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_RES4_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_RES5_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_RES6_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_RES7_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_RES8_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_SHADOW_REG_EMPTY_RES9_E,


        /* Indexes 672 - 703           */
    /* EPF ExRMON Total Samp full Interrupt Low ports 0-30 */
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_SUM_LOW_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT0_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT1_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT2_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT3_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT4_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT5_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT6_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT7_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT8_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT9_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT10_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT11_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT12_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT13_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT14_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT15_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT16_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT17_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT18_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT19_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT20_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT21_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT22_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT23_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT24_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT25_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT26_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT27_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT28_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT29_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT30_E,

    /* Indexes 704 - 735           */
    /* EPF EXRMON Total Samp full Interrupt Low ports 31-51 */
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_SUM_HIGH_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT31_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT32_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT33_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT34_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT35_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT36_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT37_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT38_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT39_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT40_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT41_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT42_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT43_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT44_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT45_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT46_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT47_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT48_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT49_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT50_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_PORT51_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_RES0_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_RES1_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_RES2_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_RES3_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_RES4_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_RES5_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_RES6_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_RES7_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_RES8_E,
    PRV_CPSS_TG_XG_EPF_EXRMON_TOTAL_SAMP_FULL_RES9_E,

    PRV_CPSS_TG_XG_LAST_INT         /* should be always last in enum */

} PRV_CPSS_TG_XG_INT_CAUSE_ENT;

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* __prvCpssDrvExMxEventsTigerh */

